{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,10,23]],"date-time":"2026-10-23T11:58:59Z","timestamp":1792756739811,"version":"4.5.0"},"reference-count":30,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2015,1,1]],"date-time":"2015-01-01T00:00:00Z","timestamp":1420070400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2015]]},"DOI":"10.1109\/tvlsi.2015.2496976","type":"journal-article","created":{"date-parts":[[2015,11,20]],"date-time":"2015-11-20T20:23:53Z","timestamp":1448051033000},"page":"1-12","source":"Crossref","is-referenced-by-count":2,"title":["Understanding the Relation Between the Performance and Reliability of NAND Flash\/SCM Hybrid Solid-State Drive"],"prefix":"10.1109","author":[{"given":"Shuhei","family":"Tanakamaru","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Shogo","family":"Hosaka","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Koh","family":"Johguchi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hirofumi","family":"Takishita","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ken","family":"Takeuchi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref30","first-page":"243","article-title":"LDPC-in-SSD: Making advanced error correction codes work effectively in solid state drives","author":"zhao","year":"2013","journal-title":"Proc 11th USENIX Conf File Storage Technol"},{"key":"ref10","first-page":"422","article-title":"A 19 nm 112.8 mm2 64 Gb multi-level flash memory with 400 Mb\/s\/pin 1.8 V toggle mode interface","author":"shibata","year":"2012","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref11","first-page":"326","article-title":"A 128 Gb MLC NAND-flash device using 16 nm planar cell","author":"helm","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref12","first-page":"328","article-title":"A 93.4 mm2 64 Gb MLC NAND-flash memory with 16 nm CMOS technology","author":"choi","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/4.705361"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2014.6849389"},{"key":"ref15","first-page":"5.2.1","article-title":"25 nm 64 Gb MLC NAND technology and scaling challenges (invited paper)","author":"prall","year":"2010","journal-title":"IEEE Int Electron Devices Meeting Tech Dig"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/GLOCOMW.2010.5700263"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2013.2281941"},{"key":"ref18","first-page":"426","article-title":"6.4 Gb\/s multi-threaded BCH encoder and decoder for multi-channel SSD controllers","author":"lee","year":"2012","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2013.2268111"},{"key":"ref28","year":"2015","journal-title":"MSR Cambridge Traces"},{"key":"ref4","first-page":"338","article-title":"A 16 Gb ReRAM with 200 MB\/s write and 1 GB\/s read in 27 nm technology","author":"fackenthal","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref27","year":"2015","journal-title":"Tpcc-mysql"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2013.6487708"},{"key":"ref6","first-page":"268","article-title":"A 90 nm 4 Mb embedded phase-change memory with 1.2 V 12 ns read access time and 1 MB\/s write throughput","author":"de sandre","year":"2010","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref29","article-title":"Low density parity check (LDPC) codes and the need for stronger ECC","author":"motwani","year":"2011","journal-title":"Proc Flash Memory Summit"},{"key":"ref5","first-page":"46","article-title":"A 20 nm 1.8 V 8 Gb PRAM with 40 MB\/s program bandwidth","author":"choi","year":"0","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref8","first-page":"262","article-title":"A scalable shield-bitline-overdrive technique for 1.3 V chain FeRAM","author":"takashima","year":"2010","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref7","first-page":"224","article-title":"Cycling endurance optimization scheme for 1 Mb STT-MRAM in 40 nm technology","author":"yu","year":"2013","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref2","first-page":"210","article-title":"A 130.7 mm2 2-layer 32 Gb ReRAM memory device in 24 nm technology","author":"liu","year":"2013","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2010.5619747"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2012.6243826"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ICEP-IAAC.2015.7111027"},{"key":"ref22","first-page":"1","article-title":"A 64 Gb NAND flash memory with 800 MB\/s synchronous DDR interface","author":"huh","year":"2012","journal-title":"Proc 4th IEEE Int Memory Workshop"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2013.6582099"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/RELPHY.2008.4558857"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2009.5424213"},{"key":"ref26","year":"2015","journal-title":"UMass Trace Repository"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488939"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/4359553\/7332804.pdf?arnumber=7332804","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:46:06Z","timestamp":1642005966000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7332804\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015]]},"references-count":30,"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2015.2496976","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015]]}}}