{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,10,2]],"date-time":"2026-10-02T02:48:53Z","timestamp":1790909333488,"version":"4.1.0"},"reference-count":45,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2016,6,1]],"date-time":"2016-06-01T00:00:00Z","timestamp":1464739200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100001348","name":"Research Grant for the Human-Centered Cyber-Physical Systems Programme within the Advanced Digital Sciences Center through the Agency for Science, Technology and Research, Singapore","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100001348","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2016,6]]},"DOI":"10.1109\/tvlsi.2015.2497259","type":"journal-article","created":{"date-parts":[[2015,12,9]],"date-time":"2015-12-09T04:36:34Z","timestamp":1449635794000},"page":"2220-2233","source":"Crossref","is-referenced-by-count":21,"title":["FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow"],"prefix":"10.1109","volume":"24","author":[{"given":"Yao","family":"Chen","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Swathi T.","family":"Gurumani","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yun","family":"Liang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Guofeng","family":"Li","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Donghui","family":"Guo","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2908-2225","authenticated-orcid":false,"given":"Kyle","family":"Rupnow","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Deming","family":"Chen","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-10877-8_6"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669143"},{"key":"ref33","article-title":"Efficient microarchitecture for network-on-chip routers","author":"becker","year":"2012"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593117"},{"key":"ref31","doi-asserted-by":"crossref","first-page":"1245","DOI":"10.7873\/DATE.2015.0694","article-title":"Malleable NoC: Dark Silicon Inspired Adaptable Network-on-Chip","author":"haseeb bokhari","year":"2015","journal-title":"Design Automation Test in Europe Conference Exhibition (DATE)"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744912"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2002.1016885"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2011.25"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/1057661.1057769"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145703"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2010.93"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.27"},{"key":"ref11","year":"2015","journal-title":"Altera SDK for OpenCL"},{"key":"ref12","first-page":"3","article-title":"Kiwi: Synthesis of FPGA circuits from parallel programs","author":"greaves","year":"2008","journal-title":"Proc Int Symp Field-Program Custom Comput Mach (FCCM)"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2110592"},{"key":"ref14","year":"2015","journal-title":"Cadence Introduces New High-Level Synthesis Technology"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/SASP.2009.5226333"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2011.29"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488747"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2013.6509613"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2013.6645496"},{"key":"ref28","first-page":"98","article-title":"An 80-tile 1.28TFLOPS network-on-chip in 65 nm CMOS","author":"vangal","year":"2007","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref4","year":"2015","journal-title":"Catapult C Synthesis"},{"key":"ref27","first-page":"914","article-title":"SUNMAP: a tool for automatic topology selection and generation for NoCs","author":"murali","year":"2004","journal-title":"Proceedings 41st Design Automation Conference 2004 DAC"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/289423.289440"},{"key":"ref6","year":"2013","journal-title":"Vivado High-Level Synthesis"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763202"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950423"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2013.6645541"},{"key":"ref7","year":"2014","journal-title":"Synphony C Compiler"},{"key":"ref2","first-page":"714","article-title":"C $\\lambda $ aSH: Structural descriptions of synchronous hardware using Haskell","author":"baaij","year":"2010","journal-title":"Proc Euromicro Conf Digital Syst Design Architect Methods Tools (DSD)"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2012.6339272"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1869459.1869469"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2006.243857"},{"key":"ref45","article-title":"An analytical model of logic resource utilization for FPGA architecture development","author":"lam","year":"2010"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2007.4380772"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/MCAS.2004.1330747"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/GCIS.2009.110"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.99"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1145\/2206781.2206797"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2007.31"},{"key":"ref44","year":"2011","journal-title":"7 Series FPGAs Memory Interface Solutions"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2011.5770723"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-02094-0_7"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20050175"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7476004\/07349212.pdf?arnumber=7349212","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:46:06Z","timestamp":1641987966000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7349212\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,6]]},"references-count":45,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2015.2497259","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,6]]}}}