{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:21:30Z","timestamp":1740133290615,"version":"3.37.3"},"reference-count":33,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2015,1,1]],"date-time":"2015-01-01T00:00:00Z","timestamp":1420070400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"Division of Computing and Communication Foundations through the National Science Foundation","award":["1115663"],"award-info":[{"award-number":["1115663"]}]},{"DOI":"10.13039\/100007245","name":"Microelectronics Advanced Research Corporation","doi-asserted-by":"crossref","award":["2198.001"],"award-info":[{"award-number":["2198.001"]}],"id":[{"id":"10.13039\/100007245","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2015]]},"DOI":"10.1109\/tvlsi.2015.2501900","type":"journal-article","created":{"date-parts":[[2015,12,17]],"date-time":"2015-12-17T14:41:04Z","timestamp":1450363264000},"page":"1-13","source":"Crossref","is-referenced-by-count":8,"title":["Incorporating Process Variations Into SRAM Electromigration Reliability Assessment Using Atomic Flux Divergence"],"prefix":"10.1109","author":[{"given":"Zhong","family":"Guan","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Malgorzata","family":"Marek-Sadowska","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-19568-6_1"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1016\/j.msea.2005.10.079"},{"key":"ref31","first-page":"165","article-title":"Compact modeling and SPICE-based simulation for electrothermal analysis of multilevel ULSI interconnects","author":"chiang","year":"2001","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Design (ICCAD)"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2013.6691144"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TSM.2008.2004323"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2043694"},{"journal-title":"Process integration devices and structures (PIDS)","year":"2012","key":"ref12"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ASQED.2009.5206305"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2011.5783112"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2007.4405720"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ACQED.2012.6320474"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/2451916.2451925"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/16.278507"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/T-ED.1969.16754"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2012.6241869"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1088\/0034-4885\/52\/3\/002"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2020721"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/RELPHY.2006.251228"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2013.6523624"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1063\/1.2761434"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1989.203510"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/IITC.2014.6831886"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2014.6783395"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2006.229176"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/16.333844"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2014.2360779"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1063\/1.322842"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/16.725264"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1063\/1.1418034"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2006.884077"},{"key":"ref23","doi-asserted-by":"crossref","first-page":"108","DOI":"10.1109\/66.827350","article-title":"modeling of interconnect capacitance, delay, and crosstalk in vlsi","volume":"13","author":"wong","year":"2000","journal-title":"IEEE Transactions on Semiconductor Manufacturing"},{"article-title":"Advanced MOSFET designs and implications for SRAM scaling","year":"2011","author":"shin","key":"ref26"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2007.4418975"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/4359553\/7360238.pdf?arnumber=7360238","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:46:06Z","timestamp":1641987966000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7360238\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015]]},"references-count":33,"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2015.2501900","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2015]]}}}