{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,25]],"date-time":"2025-10-25T12:19:15Z","timestamp":1761394755416,"version":"3.37.3"},"reference-count":22,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2016,7,1]],"date-time":"2016-07-01T00:00:00Z","timestamp":1467331200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100012226","name":"Fundamental Research Funds for the Central Universities","doi-asserted-by":"crossref","award":["N140403003"],"award-info":[{"award-number":["N140403003"]}],"id":[{"id":"10.13039\/501100012226","id-type":"DOI","asserted-by":"crossref"}]},{"name":"Doctoral Scientific Research Foundation of Liaoning Province","award":["20141015"],"award-info":[{"award-number":["20141015"]}]},{"name":"National Basic Research Program of China (973)","award":["2014CB360509"],"award-info":[{"award-number":["2014CB360509"]}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61472072","61501103"],"award-info":[{"award-number":["61472072","61501103"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2016,7]]},"DOI":"10.1109\/tvlsi.2015.2508038","type":"journal-article","created":{"date-parts":[[2016,1,6]],"date-time":"2016-01-06T19:10:39Z","timestamp":1452107439000},"page":"2449-2461","source":"Crossref","is-referenced-by-count":7,"title":["Design and FPGA Implementation of a Reconfigurable 1024-Channel Channelization Architecture for SDR Application"],"prefix":"10.1109","volume":"24","author":[{"given":"Xue","family":"Liu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ze-Ke","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Qing-Xu","family":"Deng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/79.482137"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1007\/s11265-013-0840-5"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/78.554309"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/49.761035"},{"key":"ref14","doi-asserted-by":"crossref","first-page":"577","DOI":"10.1109\/82.769806","article-title":"Signed power-of-two term allocation scheme for the design of digital filters","volume":"46","author":"lim","year":"1999","journal-title":"IEEE Trans Circuits Syst II Analog Digit Signal Process"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/82.466647"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2006.886003"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/LSP.2003.813681"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TASC.2007.898255"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2007.902608"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1049\/ic.2003.0326"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"386","DOI":"10.1007\/BF02995169","article-title":"Channelization for software defined base-stations","volume":"57","author":"hentschel","year":"2002","journal-title":"Ann Telecommun"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cds.2010.0010"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TAES.2011.5751255"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1007\/s11265-011-0579-9"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/s11265-008-0327-y"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2319335"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TAES.2005.1541437"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TSP.2004.834242"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/82.782046"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1988.15483"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2002.807574"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7498705\/07373685.pdf?arnumber=7373685","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,1]],"date-time":"2022-06-01T02:02:27Z","timestamp":1654048947000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7373685\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,7]]},"references-count":22,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2015.2508038","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2016,7]]}}}