{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,26]],"date-time":"2025-09-26T13:18:40Z","timestamp":1758892720256},"reference-count":30,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2016,8,1]],"date-time":"2016-08-01T00:00:00Z","timestamp":1470009600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2016,8]]},"DOI":"10.1109\/tvlsi.2016.2523499","type":"journal-article","created":{"date-parts":[[2016,2,16]],"date-time":"2016-02-16T19:15:48Z","timestamp":1455650148000},"page":"2726-2734","source":"Crossref","is-referenced-by-count":12,"title":["Enhanced Built-In Self-Repair Techniques for Improving Fabrication Yield and Reliability of Embedded Memories"],"prefix":"10.1109","volume":"24","author":[{"given":"Shyue-Kung","family":"Lu","sequence":"first","affiliation":[]},{"given":"Cheng-Ju","family":"Tsai","sequence":"additional","affiliation":[]},{"given":"Masaki","family":"Hashizume","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TR.2013.2240901"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2001.966724"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1270863"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2008996"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2210420"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.863189"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2007.10"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2288637"},{"key":"ref17","first-page":"234","article-title":"A memory failure pattern analyzer for memory diagnosis and repair","author":"lin","year":"2012","journal-title":"Proc IEEE VLSI Test Symp (VTS)"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.2004.1299258"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.1987.295111"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2012.6401576"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MTDT.2004.1327992"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/24.273588"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MTDT.2004.1327984"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2009.83"},{"key":"ref29","first-page":"81","article-title":"An integrated ECC and redundancy repair scheme for memory reliability enhancement","author":"su","year":"2005","journal-title":"Proc IEEE Int Symp Defect Fault Tolerance VLSI Syst (DFT)"},{"key":"ref5","first-page":"895","article-title":"At-speed built-in self-repair analyzer for embedded word-oriented memories","author":"du","year":"2004","journal-title":"Proc IEEE Int Conf VLSI Design"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TR.2003.821925"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2009.37"},{"key":"ref2","author":"wang","year":"2006","journal-title":"VLSI Test Principles and Architectures Design for Testability"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894250"},{"key":"ref1","year":"2009","journal-title":"International Technology Roadmap for Semiconductors (ITRS)"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.69"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763257"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TR.2008.2006470"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1147\/rd.144.0395"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1002\/j.1538-7305.1950.tb00463.x"},{"key":"ref26","author":"lin","year":"2004","journal-title":"Error Control Coding Fundamentals and Applications"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2007.70773"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7519042\/07407668.pdf?arnumber=7407668","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:43:31Z","timestamp":1642005811000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7407668\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,8]]},"references-count":30,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2016.2523499","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,8]]}}}