{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,25]],"date-time":"2026-04-25T08:42:01Z","timestamp":1777106521948,"version":"3.51.4"},"reference-count":42,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2016,10,1]],"date-time":"2016-10-01T00:00:00Z","timestamp":1475280000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2016,10]]},"DOI":"10.1109\/tvlsi.2016.2537846","type":"journal-article","created":{"date-parts":[[2016,3,21]],"date-time":"2016-03-21T18:56:45Z","timestamp":1458586605000},"page":"3145-3155","source":"Crossref","is-referenced-by-count":4,"title":["Fixation Ratio of Error Location-Aware Strategy for Increased Reliable Retention Time of Flash Memory"],"prefix":"10.1109","volume":"24","author":[{"given":"Debao","family":"Wei","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Liyan","family":"Qiao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shiyuan","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiyuan","family":"Peng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2157183"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2015666"},{"key":"ref33","year":"2014","journal-title":"Zynq-7000 All Programmable SoC Overview"},{"key":"ref32","article-title":"Flash file system","author":"ban","year":"1995"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/1244002.1244248"},{"key":"ref30","first-page":"22","year":"2011"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/SIPS.2006.352599"},{"key":"ref36","first-page":"1","article-title":"Optimizing NAND flash-based SSDs via retention relaxation","volume":"11","author":"liu","year":"2012","journal-title":"Target"},{"key":"ref35","first-page":"1","year":"2012"},{"key":"ref34","year":"2011","journal-title":"Asynchronous\/Synchronous NAND Flash Datasheet"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TSP.2012.2222399"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2009.27"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"1183","DOI":"10.1109\/TVLSI.2013.2264687","article-title":"High-throughput and low-complexity BCH decoding architecture for solid-state drives","volume":"22","author":"lee","year":"2014","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2265314"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228401"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2014.2347929"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2014.6742955"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1016\/j.sse.2013.12.004"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2479250"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6168954"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2012.6378623"},{"key":"ref28","first-page":"1","article-title":"A hardware-software co-design experiments platform for NAND flash based on Zynq","author":"wei","year":"2014","journal-title":"Proc IEEE 20th Int Conf Embedded Real-Time Comput Syst Appl (RTCSA)"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2003.820645"},{"key":"ref27","first-page":"140","article-title":"Error analysis and retention-aware error management for NAND flash memory","volume":"17","author":"cai","year":"2013","journal-title":"Intel Technol J"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.266"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2011.5746283"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2013.6638108"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056062"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2014.6858406"},{"key":"ref7","first-page":"26","article-title":"Digital rosetta stone: A sealed permanent memory with inductive-coupling power and data link","author":"yuxiang","year":"2009","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref2","first-page":"2e.1.1","article-title":"Scaling and reliability of NAND flash devices","author":"park","year":"2014","journal-title":"IEEE Proc Int Rel Phys Symp (IRPS)"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2280078"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2380640"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2014.6881473"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/2591513.2591594"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/2591971.2591994"},{"key":"ref42","year":"2003","journal-title":"Iometer User’s Guide"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/RELPHY.2008.4558857"},{"key":"ref41","year":"2014","journal-title":"Open NAND FLash Interface Specification Revision 2 2"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2014.2345387"},{"key":"ref26","doi-asserted-by":"crossref","first-page":"635","DOI":"10.1109\/LED.2010.2047235","article-title":"Position-dependent threshold-voltage variation by random telegraph noise in NAND flash memory strings","volume":"31","author":"joe","year":"2010","journal-title":"IEEE Electron Device Lett"},{"key":"ref25","first-page":"521","article-title":"Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis","author":"cai","year":"2012","journal-title":"Proc Design Autom Test Eur Conf Exhibition (DATE)"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7575595\/07437486.pdf?arnumber=7437486","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:07:42Z","timestamp":1642003662000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7437486\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,10]]},"references-count":42,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2016.2537846","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,10]]}}}