{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:21:33Z","timestamp":1740133293355,"version":"3.37.3"},"reference-count":35,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2016,10,1]],"date-time":"2016-10-01T00:00:00Z","timestamp":1475280000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100003621","name":"Center for Integrated Smart Sensors within the Ministry of Science, ICT and Future Planning through the Global Frontier Project","doi-asserted-by":"publisher","award":["CISS-2013M3A6A6073718"],"award-info":[{"award-number":["CISS-2013M3A6A6073718"]}],"id":[{"id":"10.13039\/501100003621","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2016,10]]},"DOI":"10.1109\/tvlsi.2016.2540069","type":"journal-article","created":{"date-parts":[[2016,3,24]],"date-time":"2016-03-24T18:22:20Z","timestamp":1458843740000},"page":"3118-3131","source":"Crossref","is-referenced-by-count":3,"title":["Hybrid L2 NUCA Design and Management Considering Data Access Latency, Energy Efficiency, and Storage Lifetime"],"prefix":"10.1109","volume":"24","author":[{"given":"Seunghan","family":"Lee","sequence":"first","affiliation":[]},{"given":"Kyungsu","family":"Kang","sequence":"additional","affiliation":[]},{"given":"Jongpil","family":"Jung","sequence":"additional","affiliation":[]},{"given":"Chong-Min","family":"Kyung","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"Performance application programming interface","year":"2016","key":"ref33"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/291006.291044"},{"key":"ref31","first-page":"111","article-title":"Fair cache sharing and partitioning in a chip multiprocessor architecture","author":"kim","year":"2004","journal-title":"Proc 13th PACT"},{"year":"2016","key":"ref30"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/373574.373578"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/1150019.1136497"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1152154.1152161"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6169036"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2012.6176518"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555758"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2483028.2483060"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.179"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/2333660.2333717"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605420"},{"key":"ref18","first-page":"69","article-title":"Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs","author":"mishra","year":"2011","journal-title":"2011 38th Annual International Symposium on Computer Architecture (ISCA) ISCA"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/2483028.2483052"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1147\/sj.92.0078"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2014.6742958"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/90.879346"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798259"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/VLSISoC.2011.6081626"},{"article-title":"Evaluating future microprocessors: The SimpleScalar tool set","year":"1996","author":"burger","key":"ref29"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2011.6105304"},{"key":"ref8","first-page":"45","article-title":"Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design","author":"chen","year":"2012","journal-title":"Proc DATE"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555761"},{"key":"ref2","first-page":"469","article-title":"McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures","author":"li","year":"2009","journal-title":"Proc of the 42nd MICRO"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2009.4796486"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1183401.1183428"},{"key":"ref20","doi-asserted-by":"crossref","first-page":"554","DOI":"10.1145\/1391469.1391610","article-title":"circuit and microarchitecture evaluation of 3d stacking magnetic ram (mram) as a universal memory replacement","author":"xiangyu dong","year":"2008","journal-title":"2008 45th ACM\/IEEE Design Automation Conference DAC"},{"key":"ref22","first-page":"125","article-title":"Latency-aware utility-based NUCA cache partitioning in 3D-stacked multi-processor systems","author":"jung","year":"2010","journal-title":"Proc 18th VLSI-SoC"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.49"},{"journal-title":"Intel Atom Processor","year":"2016","key":"ref24"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/1973009.1973028"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2185930"},{"key":"ref25","first-page":"256","article-title":"A sub-1 W to 2 W low-power IA processor for mobile Internet devices and ultra-mobile PCs in 45 nm hi- $\\kappa $ metal gate CMOS","author":"gerosa","year":"2008","journal-title":"Proc ISSCC"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7575595\/07440851.pdf?arnumber=7440851","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:07:42Z","timestamp":1642003662000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7440851\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,10]]},"references-count":35,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2016.2540069","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2016,10]]}}}