{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:21:34Z","timestamp":1740133294238,"version":"3.37.3"},"reference-count":24,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2016,11,1]],"date-time":"2016-11-01T00:00:00Z","timestamp":1477958400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100004663","name":"Ministry of Science and Technology, Taiwan","doi-asserted-by":"publisher","award":["MOST 103-2221-E-011-161-MY3"],"award-info":[{"award-number":["MOST 103-2221-E-011-161-MY3"]}],"id":[{"id":"10.13039\/501100004663","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2016,11]]},"DOI":"10.1109\/tvlsi.2016.2547958","type":"journal-article","created":{"date-parts":[[2016,4,20]],"date-time":"2016-04-20T14:24:09Z","timestamp":1461162249000},"page":"3334-3344","source":"Crossref","is-referenced-by-count":11,"title":["A 24- $\\mu \\text{W}$ 12-bit 1-MS\/s SAR ADC With Two-Step Decision DAC Switching in 110-nm CMOS"],"prefix":"10.1109","volume":"24","author":[{"given":"Yung-Hui","family":"Chung","sequence":"first","affiliation":[]},{"given":"Chia-Wei","family":"Yen","sequence":"additional","affiliation":[]},{"given":"Meng-Hsuan","family":"Wu","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2217635"},{"key":"ref11","first-page":"2231","article-title":"The swapping binary-window DAC switching technique for SAR ADCs","author":"chung","year":"2013","journal-title":"Proc IEEE Int Symp Circuits Syst"},{"key":"ref12","first-page":"176","article-title":"A 1.2 V 10 b 20 MSample\/s non-binary successive approximation ADC in \n$0.13~\\mu $\nm CMOS","author":"kuttner","year":"2002","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref13","first-page":"386","article-title":"A 10 b 100 MS\/s 1.13 mW SAR ADC with binary-scaled error compensation","author":"liu","year":"2010","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2151450"},{"key":"ref15","first-page":"1","article-title":"A \n$24~\\mu $\nW 12 b 1 MS\/s 68.3 dB SNDR SAR ADC with two-step decision DAC switching","author":"chung","year":"2013","journal-title":"Proc IEEE Custom Integr Circuits Conf"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2042254"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1975.1050629"},{"key":"ref18","first-page":"140","article-title":"A 500 MS\/s 5 b ADC in 65 nm CMOS","author":"ginsburg","year":"2006","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2048498"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2006.1692885"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/4.933473"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2009.5280859"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2108133"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/IPEC.2012.6522649"},{"key":"ref7","first-page":"380","article-title":"A 12 b 22.5\/45 MS\/s 3.0 mW 0.059 mm2 CMOS SAR ADC achieving over 90 dB SFDR","author":"liu","year":"2010","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref2","first-page":"118","article-title":"A \n$160~\\mu $\nA biopotential acquisition ASIC with fully integrated IA and motion-artifact suppression","author":"van helleputte","year":"2012","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2191212"},{"key":"ref9","first-page":"241","article-title":"A 1 V 11 fJ\/conversion-step 10 bit 10 MS\/s asynchronous SAR ADC in \n$0.18~\\mu $\nm CMOS","author":"liu","year":"2010","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/4.910473"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2008.4708780"},{"key":"ref21","first-page":"2014","article-title":"A split-capacitor \n${\\rm V_{cm}}$\n-based capacitor-switching scheme for low-power SAR ADCs","author":"wu","year":"2013","journal-title":"Proc IEEE Int Symp Circuits Syst"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2278471"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2340583"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7605567\/07454788.pdf?arnumber=7454788","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:42:49Z","timestamp":1641987769000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7454788\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,11]]},"references-count":24,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2016.2547958","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2016,11]]}}}