{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,20]],"date-time":"2026-06-20T16:21:39Z","timestamp":1781972499771,"version":"3.54.5"},"reference-count":38,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2016,12,1]],"date-time":"2016-12-01T00:00:00Z","timestamp":1480550400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2016,12]]},"DOI":"10.1109\/tvlsi.2016.2553106","type":"journal-article","created":{"date-parts":[[2016,4,29]],"date-time":"2016-04-29T18:45:58Z","timestamp":1461955558000},"page":"3489-3498","source":"Crossref","is-referenced-by-count":3,"title":["Designing Low Power and Durable Digital Blocks Using Shadow Nanoelectromechanical Relays"],"prefix":"10.1109","volume":"24","author":[{"given":"Sadegh","family":"Yazdanshenas","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Behnam","family":"Khaleghi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Paolo","family":"Ienne","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0264-3865","authenticated-orcid":false,"given":"Hossein","family":"Asadi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref38","year":"2013","journal-title":"Partial Reconfiguration of a Processor Peripheral Tutorial"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.19"},{"key":"ref32","first-page":"57","article-title":"Single event upset detection and correction in Virtex-4 and Virtex-5 FPGAs","author":"dutton","year":"2009","journal-title":"Proc CATA"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2012.2231881"},{"key":"ref30","article-title":"Error detection and recovery using CRC in Altera FPGA devices","year":"2008"},{"key":"ref37","year":"2010","journal-title":"Xilinx Partial Reconfiguration User Guide"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2009.2016633"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2011.69"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/1229175.1229176"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MEMSYS.2012.6170275"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2012.6176703"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429499"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/SLIP.2011.6135428"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2014.2380992"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20050176"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt.2008.0148"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/NANO.2012.6322087"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687490"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2012.74"},{"key":"ref28","article-title":"Correcting single-event upsets in Virtex-4 FPGA configuration memory","author":"carmichael","year":"2009"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1088\/0960-1317\/19\/8\/085003"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2014.2345291"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2074370"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2008.4681660"},{"key":"ref29","article-title":"SEU strategies for Virtex-5 devices","author":"chapman","year":"2010"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2007.4418930"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1723112.1723158"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2013.2252923"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2009.5424383"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2009.5424218"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"653","DOI":"10.1109\/TCAD.2012.2232707","article-title":"Combinational logic design using six-terminal NEM relays","volume":"32","author":"lee","year":"2013","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2011.6131645"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1063\/1.2892659"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1038\/nnano.2012.208"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2013.6571969"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2014.2318199"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2010.2068056"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/NEMS.2014.6908852"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7744633\/07463024.pdf?arnumber=7463024","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:13:22Z","timestamp":1642004002000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7463024\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,12]]},"references-count":38,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2016.2553106","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,12]]}}}