{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,4]],"date-time":"2026-06-04T17:16:46Z","timestamp":1780593406208,"version":"3.54.1"},"reference-count":41,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2017,1,1]],"date-time":"2017-01-01T00:00:00Z","timestamp":1483228800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2017,1]]},"DOI":"10.1109\/tvlsi.2016.2569562","type":"journal-article","created":{"date-parts":[[2016,5,30]],"date-time":"2016-05-30T18:05:52Z","timestamp":1464631552000},"page":"247-260","source":"Crossref","is-referenced-by-count":23,"title":["Soft Error Rate Reduction of Combinational Circuits Using Gate Sizing in the Presence of Process Variations"],"prefix":"10.1109","volume":"25","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-7113-5197","authenticated-orcid":false,"given":"Mohsen","family":"Raji","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Behnam","family":"Ghavami","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2068317"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2033697"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.891036"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1287\/opre.9.2.145"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1629948"},{"key":"ref30","first-page":"326","article-title":"TILOS: A posynomial programming approach to transistor sizing","author":"fishburn","year":"1985","journal-title":"Proc Int Conf Comput -Aided Design (ICCAD)"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2008.4751833"},{"key":"ref36","article-title":"Logic synthesis and optimization benchmarks user guide, version 3.0","author":"yang","year":"1991"},{"key":"ref35","first-page":"663","article-title":"A neural netlist of 10 combinational benchmark circuits and a target translator in FORTRAN","author":"brglez","year":"1985","journal-title":"Proc ISCAS"},{"key":"ref34","year":"2009","journal-title":"Nangate 45 nm Open Library"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2011.12.031"},{"key":"ref40","year":"2011","journal-title":"The EPFL Combinational Benchmark Suite"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2220386"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391703"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2014.67"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/4.982424"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775920"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382598"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065716"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2007.168"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2013.2288572"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2002.1028924"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VLSISOC.2006.313256"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2014.11.004"},{"key":"ref3","first-page":"157","article-title":"On soft error rate analysis of scaled CMOS designs&#x2014;A statistical perspective","author":"peng","year":"2009","journal-title":"Proc Int Conf Comput -Aided Design (ICCAD)"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.853696"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/EDTC.1996.494151"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2005.859577"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1640457.1640462"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2011.5770790"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2008.4700615"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.862738"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2013.2255624"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2012.2219070"},{"key":"ref22","first-page":"831","article-title":"Accurate statistical soft error rate (SSER) analysis using a quasi-Monte Carlo framework with quality cell models","author":"kuo","year":"2010","journal-title":"Proc Int Symp Quality Electronic Design (ISQED)"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2008.4681651"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.907047"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1146953"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2012.2194471"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/1366110.1366135"},{"key":"ref25","author":"papoulis","year":"2002","journal-title":"Probability random variables and stochastic processes"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7797597\/07480818.pdf?arnumber=7480818","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:12:14Z","timestamp":1642003934000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7480818\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,1]]},"references-count":41,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2016.2569562","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017,1]]}}}