{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:21:37Z","timestamp":1740133297296,"version":"3.37.3"},"reference-count":25,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2017,2,1]],"date-time":"2017-02-01T00:00:00Z","timestamp":1485907200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2017,2]]},"DOI":"10.1109\/tvlsi.2016.2574642","type":"journal-article","created":{"date-parts":[[2016,6,14]],"date-time":"2016-06-14T18:51:31Z","timestamp":1465930291000},"page":"547-555","source":"Crossref","is-referenced-by-count":2,"title":["Systematic Methodology for the Quantitative Analysis of Pipeline-Register Reliability"],"prefix":"10.1109","volume":"25","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-3774-1916","authenticated-orcid":false,"given":"Reiley","family":"Jeyapaul","sequence":"first","affiliation":[]},{"given":"Roberto","family":"Flores","sequence":"additional","affiliation":[]},{"given":"Alfonso","family":"Avila","sequence":"additional","affiliation":[]},{"given":"Aviral","family":"Shrivastava","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007145"},{"journal-title":"ARM Architecture Reference Manual","year":"2008","key":"ref11"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253181"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250719"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.9"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.18"},{"key":"ref16","first-page":"129","article-title":"Versatile prediction and fast estimation of architectural vulnerability factor from processor performance metrics","author":"duan","year":"2009","journal-title":"Proc IEEE 15th Int Symp High Perform Comput Archit (HPCA)"},{"key":"ref17","doi-asserted-by":"crossref","first-page":"323","DOI":"10.1145\/1366224.1366225","article-title":"Quantifying software vulnerability","author":"sridharan","year":"2008","journal-title":"Proc Workshop Radiation Effects and Fault Tolerance Nanometer Technologies"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1016\/j.jpdc.2012.05.002"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2016.01.012"},{"article-title":"Wire aware cache architecture","year":"2009","author":"muralimanohar","key":"ref4"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2003.821593"},{"key":"ref6","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/2024716.2024718","article-title":"The gem5 simulator","volume":"39","author":"binkert","year":"2011","journal-title":"ACM SIGARCH Comput Archit News"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2003.1261389"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.887832"},{"key":"ref7","first-page":"1","article-title":"Soft error analysis and optimizations of C-elements in asynchronous circuits","author":"vaidyanathan","year":"2006","journal-title":"2nd Workshop on System Effects of Logic Soft Errors"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2015.01.003"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2008.4523226"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"732","DOI":"10.1109\/TDMR.2014.2316505","article-title":"Soft-error performance evaluation on emerging low power devices","volume":"14","author":"liu","year":"2014","journal-title":"IEEE Trans Device Mater Rel"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/2039370.2039408"},{"journal-title":"ModelSim Advanced Simulation and Debugging","year":"2013","key":"ref22"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775927"},{"journal-title":"Amber Arm-compatible Core","year":"2013","author":"santifort","key":"ref24"},{"journal-title":"Icarus verilog","year":"2013","author":"williams","key":"ref23"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/AERO.2011.5747457"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7827022\/07491369.pdf?arnumber=7491369","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,8,18]],"date-time":"2023-08-18T22:06:57Z","timestamp":1692396417000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7491369\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,2]]},"references-count":25,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2016.2574642","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2017,2]]}}}