{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:21:37Z","timestamp":1740133297172,"version":"3.37.3"},"reference-count":39,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2017,1,1]],"date-time":"2017-01-01T00:00:00Z","timestamp":1483228800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"publisher","award":["2015-EP-2650"],"award-info":[{"award-number":["2015-EP-2650"]}],"id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2017,1]]},"DOI":"10.1109\/tvlsi.2016.2578933","type":"journal-article","created":{"date-parts":[[2016,6,24]],"date-time":"2016-06-24T18:52:36Z","timestamp":1466794356000},"page":"177-188","source":"Crossref","is-referenced-by-count":3,"title":["ENFIRE: A Spatio-Temporal Fine-Grained Reconfigurable Hardware"],"prefix":"10.1109","volume":"25","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-7288-498X","authenticated-orcid":false,"given":"Wenchao","family":"Qian","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Christopher","family":"Babecki","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Robert","family":"Karam","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Somnath","family":"Paul","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Swarup","family":"Bhunia","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2011.42"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950419"},{"journal-title":"Predictive Technology Model—Introduction","year":"2017","key":"ref33"},{"journal-title":"HSPICE","year":"2017","key":"ref32"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/2591513.2591561"},{"journal-title":"RASP—FPGA\/CPLD Technology Mapping and Synthesis Package","year":"2017","key":"ref30"},{"journal-title":"Powerplay early power estimators (epe) and power analyzer","year":"2017","key":"ref37"},{"journal-title":"VCS","year":"2017","key":"ref36"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TELFOR.2011.6143696"},{"journal-title":"Synopsys 90 nm Generic Library for Teaching IC Design","year":"0","key":"ref34"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1999.765937"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2332538"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1997.624600"},{"journal-title":"Field-Programmable Logic Appl","article-title":"Tabula, going beyond the FPGA with spacetime","year":"2012","key":"ref13"},{"key":"ref14","first-page":"328","article-title":"A 320 mV-to-1.2 V on-die fine-grained reconfigurable fabric for DSP\/media accelerators in 32nm CMOS","author":"agarwal","year":"2010","journal-title":"Proc IEEE Int Solid-State Circuits Conf"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2003.1234203"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1007\/s11227-005-0289-9"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/871506.871541"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/1344418.1344426"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2010.2041556"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/12.859540"},{"journal-title":"Quartus II Subscription Edition Software","year":"2017","key":"ref28"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2006.243769"},{"journal-title":"Berkeley Logic Interchange Format","year":"2017","key":"ref27"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/275107.275137"},{"journal-title":"Synopsys DC Ultra","year":"2017","key":"ref29"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.810003"},{"key":"ref8","first-page":"115","article-title":"DPGA utilization and application","author":"dehon","year":"1996","journal-title":"Proc Int Symp FPGAs"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/275107.275138"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/11847083_40"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/DELTA.2008.14"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1995.518231"},{"journal-title":"VPR and T-VPack 5 0 2 Full CAD Flow for Heterogeneous FPGAs","year":"2017","key":"ref20"},{"journal-title":"Monte Carlo Methods","year":"2013","author":"hammersley","key":"ref22"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2011.2165232"},{"journal-title":"FPGA Architecture for the Challenge","year":"2017","key":"ref24"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/272991.272995"},{"journal-title":"Graphviz—Graph Visualization Software","year":"2017","key":"ref26"},{"journal-title":"Benchmark Archives at CBL","year":"2017","key":"ref25"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7797597\/07499840.pdf?arnumber=7499840","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:12:14Z","timestamp":1642003934000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7499840\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,1]]},"references-count":39,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2016.2578933","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2017,1]]}}}