{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T10:46:21Z","timestamp":1761648381981,"version":"3.37.3"},"reference-count":46,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2017,1,1]],"date-time":"2017-01-01T00:00:00Z","timestamp":1483228800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2017,1,1]],"date-time":"2017-01-01T00:00:00Z","timestamp":1483228800000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2017,1,1]],"date-time":"2017-01-01T00:00:00Z","timestamp":1483228800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2017,1,1]],"date-time":"2017-01-01T00:00:00Z","timestamp":1483228800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["0903549","1018972","CAREER 0546907"],"award-info":[{"award-number":["0903549","1018972","CAREER 0546907"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"publisher","award":["CSR 1659","GRC 1971","GRC 2321"],"award-info":[{"award-number":["CSR 1659","GRC 1971","GRC 2321"]}],"id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]},{"name":"ST Microelectronics"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2017,1]]},"DOI":"10.1109\/tvlsi.2016.2580142","type":"journal-article","created":{"date-parts":[[2016,7,12]],"date-time":"2016-07-12T20:38:21Z","timestamp":1468355901000},"page":"100-113","source":"Crossref","is-referenced-by-count":10,"title":["Hybrid Hardware\/Software Floating-Point Implementations for Optimized Area and Throughput Tradeoffs"],"prefix":"10.1109","volume":"25","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0833-0392","authenticated-orcid":false,"given":"Jon J.","family":"Pimentel","sequence":"first","affiliation":[]},{"given":"Brent","family":"Bohnenstiehl","sequence":"additional","affiliation":[]},{"given":"Bevan M.","family":"Baas","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/BIOCAS.2010.5709624"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2008.4751869"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/40.612224"},{"key":"ref32","first-page":"226","article-title":"Implementation of single precision floating point square root on FPGAs","author":"li","year":"1997","journal-title":"Proc 5th Annu IEEE Symp Field-Program Custom Comput Mach"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1007\/BF02307376"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.2005.6"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2011.2133290"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2008.4585936"},{"journal-title":"IA-64 and Elementary Functions Speed and Precision","year":"2000","author":"markstein","key":"ref35"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1007\/BF02239012"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2010.139"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1147\/rd.341.0059"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2010.121"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.912041"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/78.492531"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2012.28"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/SiPS.2013.6674498"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1155\/S1110865702205090"},{"key":"ref17","first-page":"-869i","article-title":"Low cost floating-point unit design for audio applications","volume":"1","author":"lee","year":"2002","journal-title":"Proc IEEE Int Symp Circuits Syst (ISCAS)"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.2015.7421230"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/92.845894"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/12.609274"},{"journal-title":"Floating-Point Arithmetic","year":"2015","key":"ref4"},{"article-title":"Reconfigurable custom floating-point instructions","year":"2009","author":"jin","key":"ref27"},{"article-title":"An investigation of the Blackfin\/uClinux combination as a candidate software radio processor","year":"2006","author":"shajedul hasan","key":"ref3"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.916616"},{"article-title":"Architectures for floating-point division","year":"2005","author":"nikmehr","key":"ref29"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.2003.1207669"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2072996"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2013772"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2011.6043260"},{"journal-title":"The Industry’s First Floating-Point FPGA Altera","year":"2015","key":"ref9"},{"journal-title":"Handbook of Floating-Point Arithmetic","year":"2009","author":"muller","key":"ref1"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1007\/s10766-007-0034-5"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.870924"},{"article-title":"An analysis of division algorithms and implementations","year":"1995","author":"oberman","key":"ref45"},{"year":"2008","key":"ref22"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1007\/s11265-010-0561-y"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1007\/978-0-387-34047-0"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/279232.279237"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1147\/rd.341.0071"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.2005.1599982"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/HLDVT.2003.1252469"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/12.565590"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.2014.7094784"},{"journal-title":"Digital System Designs and Practices Using Verilog HDL and FPGAs","year":"2008","author":"lin","key":"ref25"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/ieeexplore.ieee.org\/ielaam\/92\/7797597\/7509625-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7797597\/07509625.pdf?arnumber=7509625","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,8]],"date-time":"2022-04-08T18:48:33Z","timestamp":1649443713000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7509625\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,1]]},"references-count":46,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2016.2580142","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2017,1]]}}}