{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,8]],"date-time":"2025-11-08T13:00:23Z","timestamp":1762606823778,"version":"3.37.3"},"reference-count":19,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2017,2,1]],"date-time":"2017-02-01T00:00:00Z","timestamp":1485907200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100004663","name":"Ministry of Science and Technology, Taiwan","doi-asserted-by":"publisher","award":["MOST 103-2220-E-006-007","MOST 104-2220-E-006-006"],"award-info":[{"award-number":["MOST 103-2220-E-006-007","MOST 104-2220-E-006-006"]}],"id":[{"id":"10.13039\/501100004663","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2017,2]]},"DOI":"10.1109\/tvlsi.2016.2586184","type":"journal-article","created":{"date-parts":[[2016,7,20]],"date-time":"2016-07-20T18:22:46Z","timestamp":1469038966000},"page":"621-634","source":"Crossref","is-referenced-by-count":2,"title":["Analyses of Splittable Amplifier Technique and Cancellation of Memory Effect for Opamp Sharing"],"prefix":"10.1109","volume":"25","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9217-3424","authenticated-orcid":false,"given":"I-Jen","family":"Chao","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bin-Da","family":"Liu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Soon-Jyh","family":"Chang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chun-Yueh","family":"Huang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hsin-Wen","family":"Ting","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"crossref","first-page":"168","DOI":"10.1109\/TCSII.2010.2041815","article-title":"Bias-and-input interchanging technique for cyclic\/pipelined ADCs with opamp sharing","volume":"57","author":"kuo","year":"2010","journal-title":"IEEE Trans Circuits Syst II Exp Briefs"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2050915"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2052376"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2011.2112591"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1587\/transele.E94.C.1282"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2013.2252643"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2011.2149130"},{"key":"ref17","first-page":"60","author":"razavi","year":"2001","journal-title":"Design of Analog CMOS Integrated Circuits"},{"article-title":"Common-mode output sensing circuit","year":"1999","author":"garrity","key":"ref18"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2003.820253"},{"key":"ref4","first-page":"501","article-title":"A partially switched-opamp technique for high-speed low-power pipelined analog-to-digital converters","volume":"53","author":"kim","year":"2006","journal-title":"IEEE Trans Circuits Syst I Reg Papers"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/4.735528"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2012.2206509"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/4.557628"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2010.2092170"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2199669"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/4.597284"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/4.297698"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.891718"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7827022\/07517306.pdf?arnumber=7517306","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:20:17Z","timestamp":1642004417000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7517306\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,2]]},"references-count":19,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2016.2586184","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2017,2]]}}}