{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,11]],"date-time":"2025-11-11T15:43:47Z","timestamp":1762875827013,"version":"3.37.3"},"reference-count":21,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2017,2,1]],"date-time":"2017-02-01T00:00:00Z","timestamp":1485907200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2017,2,1]],"date-time":"2017-02-01T00:00:00Z","timestamp":1485907200000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2017,2,1]],"date-time":"2017-02-01T00:00:00Z","timestamp":1485907200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2017,2,1]],"date-time":"2017-02-01T00:00:00Z","timestamp":1485907200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CNS-0953468","CNS-1423290","CNS-1018621"],"award-info":[{"award-number":["CNS-0953468","CNS-1423290","CNS-1018621"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2017,2]]},"DOI":"10.1109\/tvlsi.2016.2586379","type":"journal-article","created":{"date-parts":[[2016,8,9]],"date-time":"2016-08-09T18:11:51Z","timestamp":1470766311000},"page":"462-475","source":"Crossref","is-referenced-by-count":23,"title":["Energy-Efficient Reduce-and-Rank Using Input-Adaptive Approximations"],"prefix":"10.1109","volume":"25","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-8848-1069","authenticated-orcid":false,"given":"Arnab","family":"Raha","sequence":"first","affiliation":[]},{"given":"Swagath","family":"Venkataramani","sequence":"additional","affiliation":[]},{"given":"Vijay","family":"Raghunathan","sequence":"additional","affiliation":[]},{"given":"Anand","family":"Raghunathan","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763130"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228509"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1878921.1878948"},{"key":"ref13","first-page":"1","article-title":"ASLAN: Synthesis of approximate sequential circuits","author":"ranjan","year":"2014","journal-title":"Proc DATE"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2011.51"},{"key":"ref15","first-page":"361:1","article-title":"ABACUS: A technique for automated behavioral synthesis of approximate computing circuits","author":"nepal","year":"2014","journal-title":"Proc DATE"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763153"},{"key":"ref17","first-page":"957","article-title":"Approximate logic synthesis for error tolerant applications","author":"shin","year":"2010","journal-title":"Proc DATE"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2014.62"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2424212"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1806596.1806620"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2025113.2025133"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540710"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024863"},{"key":"ref8","first-page":"1","article-title":"A new circuit simplification method for error tolerant applications","author":"shin","year":"2011","journal-title":"Proc DATE"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540711"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837492"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2005.58"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228504"},{"key":"ref20","first-page":"665","article-title":"Quality configurable reduce-and-rank for energy efficient approximate computing","author":"raha","year":"2015","journal-title":"Proc DATE"},{"journal-title":"Design Compiler","year":"2012","key":"ref21"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/ieeexplore.ieee.org\/ielaam\/92\/7827022\/7536634-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7827022\/07536634.pdf?arnumber=7536634","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,8]],"date-time":"2022-04-08T18:48:33Z","timestamp":1649443713000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7536634\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,2]]},"references-count":21,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2016.2586379","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2017,2]]}}}