{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,22]],"date-time":"2025-03-22T10:16:27Z","timestamp":1742638587142,"version":"3.37.3"},"reference-count":11,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2017,2,1]],"date-time":"2017-02-01T00:00:00Z","timestamp":1485907200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"National Research Foundation of the Ministry of Science, ICT and Future Planning, Korea","award":["NRF-2014R1A2A1A11052875"],"award-info":[{"award-number":["NRF-2014R1A2A1A11052875"]}]},{"DOI":"10.13039\/501100003836","name":"IDEC","doi-asserted-by":"crossref","id":[{"id":"10.13039\/501100003836","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2017,2]]},"DOI":"10.1109\/tvlsi.2016.2600267","type":"journal-article","created":{"date-parts":[[2016,8,31]],"date-time":"2016-08-31T20:34:02Z","timestamp":1472675642000},"page":"788-792","source":"Crossref","is-referenced-by-count":6,"title":["All-Synthesizable Current-Mode Transmitter Driver for USB2.0 Interface"],"prefix":"10.1109","volume":"25","author":[{"given":"Kihwan","family":"Seong","sequence":"first","affiliation":[]},{"given":"Won-Cheol","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Byungsub","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Jae-Yoon","family":"Sim","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8359-0063","authenticated-orcid":false,"given":"Hong-June","family":"Park","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","first-page":"285","article-title":"A 0.011 mm2 PVT-robust fully-synthesizable CDR with a data rate of 10.05 Gb\/s in 28 nm FD SOI","author":"narayanan","year":"2014","journal-title":"Proc IEEE Asian Solid-State Circuits Conf (ASSCC)"},{"key":"ref3","first-page":"250","article-title":"A 0.032 mm\n$^{2}~3.1$\n mW synthesized pixel clock generator with 30 psrms integrated jitter and 10-to-630 MHz DCO tuning range","author":"kim","year":"2013","journal-title":"Proc IEEE Int Solid-State Circuits Conf (ISSCC)"},{"key":"ref10","first-page":"177","article-title":"A 5 Gb\/s low-power PCI express\/USB 3.0 ready PHY in 40 nm CMOS technology with high-jitter immunity","author":"lin","year":"2009","journal-title":"Proc IEEE Asian Solid-State Circuits Conf (ASSCC)"},{"journal-title":"USB2 0 Transceiver Macrocell Interface Specification Revision 1 05","year":"2001","key":"ref6"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2013.6691022"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.5573\/JSTS.2014.14.4.463"},{"key":"ref8","first-page":"309","article-title":"A UTMI-compatible physical-layer USB 2.0 transceiver chip","author":"nam","year":"2003","journal-title":"Proc IEEE Int Syst -Chip Conf (SoC)"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2013.2268571"},{"key":"ref2","first-page":"266","article-title":"A 0.0066 mm\n$^{2}~780~\\mu $\nW fully synthesizable PLL with a current-output DAC and an interpolative phase-coupled oscillator using edge-injection technique","author":"deng","year":"2014","journal-title":"Proc IEEE Int Solid-State Circuits Conf (ISSCC)"},{"key":"ref9","first-page":"152","article-title":"A highly digital 0.5-to-4 Gb\/s 1.9 mW\/Gb\/s serial-link transceiver using current-recycling in 90 nm CMOS","author":"inti","year":"2011","journal-title":"Proc IEEE Int Solid-State Circuits Conf (ISSCC)"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/4.760373"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7827022\/07557069.pdf?arnumber=7557069","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:20:16Z","timestamp":1642004416000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7557069\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,2]]},"references-count":11,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2016.2600267","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2017,2]]}}}