{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,26]],"date-time":"2025-09-26T13:30:06Z","timestamp":1758893406478,"version":"3.37.3"},"reference-count":40,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2017,3,1]],"date-time":"2017-03-01T00:00:00Z","timestamp":1488326400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2017,3]]},"DOI":"10.1109\/tvlsi.2016.2614993","type":"journal-article","created":{"date-parts":[[2016,10,28]],"date-time":"2016-10-28T18:23:40Z","timestamp":1477679020000},"page":"820-832","source":"Crossref","is-referenced-by-count":5,"title":["A Novel Cache-Utilization-Based Dynamic Voltage-Frequency Scaling Mechanism for Reliability Enhancements"],"prefix":"10.1109","volume":"25","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-5456-8393","authenticated-orcid":false,"given":"Yen-Hao","family":"Chen","sequence":"first","affiliation":[]},{"given":"Yi-Lun","family":"Tang","sequence":"additional","affiliation":[]},{"given":"Yi-Yu","family":"Liu","sequence":"additional","affiliation":[]},{"given":"Allen C.-H.","family":"Wu","sequence":"additional","affiliation":[]},{"given":"TingTing","family":"Hwang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/1785481.1785553"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.51"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1587\/transele.E96.C.528"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2010.5617629"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/12.762529"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.859029"},{"key":"ref37","first-page":"147","article-title":"Dynamic power management for multicores: Case study using the Intel SCC","author":"david","year":"2012","journal-title":"Proc VLSI Syst Chip Conf"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/1186736.1186737"},{"key":"ref35","doi-asserted-by":"crossref","first-page":"92","DOI":"10.1145\/1105734.1105747","article-title":"Multifacet&#x2019;s general execution-driven multiprocessor simulator (GEMS) toolset","volume":"33","author":"martin","year":"2005","journal-title":"ACM SIGARCH Comput Archit News"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485949"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2332267"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1145\/1840845.1840888"},{"article-title":"Ultra-low-power variationtolerant radiation-hardened cache design","year":"2013","author":"moore","key":"ref11"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.22"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2013.6575314"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669126"},{"key":"ref15","first-page":"461","article-title":"Energy-efficient cache design using variable-strength error-correcting codes","author":"alameldeen","year":"2011","journal-title":"2011 38th Annual International Symposium on Computer Architecture (ISCA) ISCA"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2012.2231013"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/1878921.1878956"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-662-45483-1_13"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669128"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2005.23"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2003.1183527"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/2504905"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1504\/IJCAET.2014.065419"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1987.1052809"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2011.18"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669151"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2187474"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908005"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.4304\/jcp.3.8.49-57"},{"key":"ref9","first-page":"388","article-title":"A 32 kb 10T subthreshold SRAM array with bit-interleaving and differential read scheme in 90 nm CMOS","author":"chang","year":"2008","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1587\/transele.E92.C.423"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749758"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2055589"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522347"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/859619.859621"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2013.6657029"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/1283780.1283825"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.30"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7862316\/07725503.pdf?arnumber=7725503","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:12:04Z","timestamp":1642003924000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7725503\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,3]]},"references-count":40,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2016.2614993","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2017,3]]}}}