{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:21:41Z","timestamp":1740133301734,"version":"3.37.3"},"reference-count":22,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2017,3,1]],"date-time":"2017-03-01T00:00:00Z","timestamp":1488326400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2017,3,1]],"date-time":"2017-03-01T00:00:00Z","timestamp":1488326400000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2017,3,1]],"date-time":"2017-03-01T00:00:00Z","timestamp":1488326400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2017,3,1]],"date-time":"2017-03-01T00:00:00Z","timestamp":1488326400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000001","name":"U.S. National Science Foundation","doi-asserted-by":"publisher","award":["1453142"],"award-info":[{"award-number":["1453142"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000185","name":"Defense Advanced Research Projects Agency","doi-asserted-by":"publisher","award":["HR0011-13-C-0003"],"award-info":[{"award-number":["HR0011-13-C-0003"]}],"id":[{"id":"10.13039\/100000185","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100004543","name":"China Scholarship Council","doi-asserted-by":"publisher","award":["201406230166"],"award-info":[{"award-number":["201406230166"]}],"id":[{"id":"10.13039\/501100004543","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2017,3]]},"DOI":"10.1109\/tvlsi.2016.2625598","type":"journal-article","created":{"date-parts":[[2016,11,16]],"date-time":"2016-11-16T22:12:04Z","timestamp":1479334324000},"page":"1032-1043","source":"Crossref","is-referenced-by-count":11,"title":["&lt;italic&gt;In Situ&lt;\/italic&gt; Error Detection Techniques in Ultralow Voltage Pipelines: Analysis and Optimizations"],"prefix":"10.1109","volume":"25","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-5108-5233","authenticated-orcid":false,"given":"Wei","family":"Jin","sequence":"first","affiliation":[]},{"given":"Seongjong","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Weifeng","family":"He","sequence":"additional","affiliation":[]},{"given":"Zhigang","family":"Mao","sequence":"additional","affiliation":[]},{"given":"Mingoo","family":"Seok","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/871506.871535"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228534"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2258831"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090638"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2011.24"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1996.488543"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/1840845.1840901"},{"key":"ref17","first-page":"291","article-title":"Analysis and optimization of in-situ error detection techniques in ultra-low-voltage pipeline","author":"seongjong","year":"2014","journal-title":"Proc IEEE\/ACM Int Symp Low Power Electron Design (ISLPED)"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2008.4586001"},{"key":"ref19","first-page":"428","article-title":"A low-power 1GHz razor FIR accelerator with time-borrow tracking pipeline and approximate error correction in 65nm CMOS","author":"whatmough","year":"2013","journal-title":"IEEE Int Solid-State Circuits Conf Dig Techn Papers (ISSCC)"},{"key":"ref4","first-page":"264","article-title":"Razor-lite: A side-channel error-detection register for timing-margin recovery in 45nm SOI CMOS","author":"kim","year":"2013","journal-title":"Proc Int Solid-State Circuits Conf"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6177103"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2079410"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2089657"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007145"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6177105"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.870912"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2034764"},{"key":"ref9","doi-asserted-by":"crossref","first-page":"199","DOI":"10.1109\/ISLPED.2013.6629294","article-title":"A pipeline architecture with 1-cycle timing error correction for low voltage operations","author":"shin","year":"2013","journal-title":"Proc Int Symp Low-Power Electronics Design"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2418713"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7417956"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2016.7573561"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/ieeexplore.ieee.org\/ielaam\/92\/7862316\/7745895-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7862316\/07745895.pdf?arnumber=7745895","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,8]],"date-time":"2022-04-08T18:48:34Z","timestamp":1649443714000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7745895\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,3]]},"references-count":22,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2016.2625598","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2017,3]]}}}