{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:21:42Z","timestamp":1740133302844,"version":"3.37.3"},"reference-count":19,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2017,4,1]],"date-time":"2017-04-01T00:00:00Z","timestamp":1491004800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"Ministry of Science, ICT, and Future Planning, South Korea, under the Information Technology Research Center support program","award":["IITP-2016-H8601-16-1011"],"award-info":[{"award-number":["IITP-2016-H8601-16-1011"]}]},{"DOI":"10.13039\/501100010418","name":"Institute for Information & Communications Technology Promotion","doi-asserted-by":"crossref","id":[{"id":"10.13039\/501100010418","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/501100001321","name":"Basic Science Research Program through NRF funded by the Ministry of Education","doi-asserted-by":"publisher","award":["2013R1A1A4A01012914"],"award-info":[{"award-number":["2013R1A1A4A01012914"]}],"id":[{"id":"10.13039\/501100001321","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003836","name":"IDEC","doi-asserted-by":"crossref","id":[{"id":"10.13039\/501100003836","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2017,4]]},"DOI":"10.1109\/tvlsi.2016.2639289","type":"journal-article","created":{"date-parts":[[2017,1,4]],"date-time":"2017-01-04T19:12:35Z","timestamp":1483557155000},"page":"1386-1396","source":"Crossref","is-referenced-by-count":4,"title":["An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb\/s Chip-to-Chip Interfaces With Source-Synchronous Clock"],"prefix":"10.1109","volume":"25","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-8096-8518","authenticated-orcid":false,"given":"Pil-Ho","family":"Lee","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0515-7598","authenticated-orcid":false,"given":"Han-Yeol","family":"Lee","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9598-6858","authenticated-orcid":false,"given":"Hyun-Bae","family":"Lee","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8680-9270","authenticated-orcid":false,"given":"Young-Chan","family":"Jang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2005716"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.870894"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"117","DOI":"10.1109\/TCSII.2008.2010189","article-title":"Jitter analysis and a benchmarking figure-of-merit for phase-locked loops","volume":"56","author":"gao","year":"2009","journal-title":"IEEE Trans Circuits Syst II Express Briefs"},{"key":"ref13","first-page":"188","article-title":"A 12Gb\/s 0.9mW\/Gb\/s wide-bandwidth injectiontype CDR in 28nm CMOS with reference-free frequency capture","author":"masuda","year":"2016","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2011.2161167"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2006.885069"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2023156"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2217873"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757530"},{"key":"ref19","first-page":"2725","article-title":"Track and hold for Giga-sample ADC applications using CMOS technology","author":"macedo","year":"2014","journal-title":"Proc IEEE Int Symp Circuits Syst"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.818569"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2185184"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TIM.2007.899843"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2265895"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.812313"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2008.4681808"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2466469"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2010.5490798"},{"key":"ref9","doi-asserted-by":"crossref","first-page":"472","DOI":"10.1109\/TCSII.2011.2158752","article-title":"A 2.4-GHz extended-range type-I $\\Sigma \\Delta $ fractional-N synthesizer with 1.8-MHz loop bandwidth and ?110-dBc\/Hz phase noise","volume":"58","author":"shekhar","year":"2011","journal-title":"IEEE Trans Circuits Syst II Express Briefs"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7882729\/07805161.pdf?arnumber=7805161","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:13:09Z","timestamp":1642003989000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7805161\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,4]]},"references-count":19,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2016.2639289","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2017,4]]}}}