{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:21:43Z","timestamp":1740133303714,"version":"3.37.3"},"reference-count":32,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2017,4,1]],"date-time":"2017-04-01T00:00:00Z","timestamp":1491004800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"special grant to Nanotechnology Research Triangle from the Indian Statistical Institute, Kolkata"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2017,4]]},"DOI":"10.1109\/tvlsi.2016.2642343","type":"journal-article","created":{"date-parts":[[2017,1,17]],"date-time":"2017-01-17T03:16:51Z","timestamp":1484623011000},"page":"1467-1476","source":"Crossref","is-referenced-by-count":3,"title":["COMEDI: Combinatorial Election of Diagnostic Vectors From Detection Test Sets for Logic Circuits"],"prefix":"10.1109","volume":"25","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-6453-4971","authenticated-orcid":false,"given":"Manjari","family":"Pradhan","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bhargab B.","family":"Bhattacharya","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1990.129886"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/54.867894"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1989.100747"},{"key":"ref10","first-page":"1","article-title":"An effective and flexible multiple defect diagnosis methodology using error propagation analysis","author":"yu","year":"2008","journal-title":"Proc IEEE Int Test Conf (ITC)"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2010.5699237"},{"key":"ref12","first-page":"12","article-title":"ATALANTA: An efficient ATPG for combinational circuits","author":"lee","year":"1993"},{"journal-title":"TetraMax ATPG","year":"2016","key":"ref13"},{"key":"ref14","doi-asserted-by":"crossref","first-page":"1048","DOI":"10.1109\/43.536711","article-title":"HOPE: An efficient parallel fault simulator for synchronous sequential circuits","volume":"15","author":"lee","year":"1996","journal-title":"IEEE Trans Comput -Aided Design Integr Circuits Syst"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2014.6818790"},{"key":"ref16","first-page":"192","article-title":"Substantial fault pair at-a-time (SFPAT): An automatic diagnostic pattern generation method","author":"ye","year":"2010","journal-title":"Proc ATS"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2015.7116269"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.2003.1183128"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1971.223129"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1270849"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2272538"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2011.6081382"},{"key":"ref3","first-page":"376","article-title":"Defect diagnosis of digital circuits using surrogate faults","author":"alagappan","year":"2013","journal-title":"Proceedings of VDAT"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.884486"},{"key":"ref29","first-page":"677","article-title":"A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran","author":"brglez","year":"1985","journal-title":"Proc ISCAS"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2533444"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2249542"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2014.22"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2015.7116270"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2011.37"},{"key":"ref1","first-page":"145","article-title":"Analyzing volume diagnosis results with statistical learning for yield improvement","author":"tang","year":"2007","journal-title":"Proc ETS"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1991.185229"},{"key":"ref22","first-page":"151","article-title":"Diagnostic test generation based on subsets of faults","author":"pomeranz","year":"2007","journal-title":"Proc ETS"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2004.1329502"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.814241"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1998.743306"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2007.78"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1268829"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7882729\/07817897.pdf?arnumber=7817897","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:13:12Z","timestamp":1642003992000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7817897\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,4]]},"references-count":32,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2016.2642343","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2017,4]]}}}