{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:21:42Z","timestamp":1740133302962,"version":"3.37.3"},"reference-count":19,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2017,1,1]],"date-time":"2017-01-01T00:00:00Z","timestamp":1483228800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"Nano\u00b7Material Technology Development Program through the National Research Foundation of Korea funded by the Ministry of Science ICT and Future Planning","award":["Contract 2016M3A7B4910575"],"award-info":[{"award-number":["Contract 2016M3A7B4910575"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2017]]},"DOI":"10.1109\/tvlsi.2016.2645384","type":"journal-article","created":{"date-parts":[[2017,1,16]],"date-time":"2017-01-16T17:26:26Z","timestamp":1484587586000},"page":"1-10;","source":"Crossref","is-referenced-by-count":3,"title":["A Fast and Reliable Cross-Point Three-State\/Cell ReRAM"],"prefix":"10.1109","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-7214-8010","authenticated-orcid":false,"given":"Soon-Chan","family":"Kwon","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jong-Min","family":"Baek","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jong-Moon","family":"Choi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4513-8532","authenticated-orcid":false,"given":"Kee-Won","family":"Kwon","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"9","article-title":"Low-voltage read\/write circuit design for transistorless ReRAM crossbar arrays in 180 nm CMOS technology","author":"sandrini","year":"2015","journal-title":"Proc IEEE Int Symp Circuits Syst"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2011.2166051"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2015.7150272"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2011.2167513"},{"key":"ref14","doi-asserted-by":"crossref","first-page":"163502-1","DOI":"10.1063\/1.4825104","article-title":"Characteristics of hafnium oxide resistance random access memory with different setting compliance current","volume":"103","author":"su","year":"2013","journal-title":"Appl Phys Lett"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2013.2261451"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2013.6582111"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2014.2316544"},{"key":"ref18","first-page":"332","article-title":"Embedded 1 Mb ReRAM in 28 nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme","author":"chang","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref19","first-page":"434","article-title":"A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time","author":"chang","year":"2012","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2010.2070830"},{"key":"ref3","first-page":"334","article-title":"Three-dimensional 128Gb MLC vertical NAND flash-memory with 24-WL stacked layers and 50MB\/s high-speed programming","author":"park","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2230515"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2010.01.022"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2013.2281767"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.810048"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2010.5488765"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/4.962291"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2016.2546199"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/4359553\/07819512.pdf?arnumber=7819512","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:39:35Z","timestamp":1641987575000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7819512\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2016.2645384","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2017]]}}}