{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,21]],"date-time":"2026-02-21T18:02:57Z","timestamp":1771696977696,"version":"3.50.1"},"reference-count":21,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2017,7,1]],"date-time":"2017-07-01T00:00:00Z","timestamp":1498867200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2017,7]]},"DOI":"10.1109\/tvlsi.2017.2677978","type":"journal-article","created":{"date-parts":[[2017,3,20]],"date-time":"2017-03-20T18:11:37Z","timestamp":1490033497000},"page":"2007-2016","source":"Crossref","is-referenced-by-count":6,"title":["A Closed-Form Expression for Minimum Operating Voltage of CMOS D Flip-Flop"],"prefix":"10.1109","volume":"25","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-0171-6679","authenticated-orcid":false,"given":"Hiroshi","family":"Fuketa","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shin-ichi","family":"O'uchi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Takashi","family":"Matsukawa","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"21","article-title":"12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (VDD) scaling from 1.2V to 310 mV enabled by contention-less flip-flops (CLFF) and separated VDD between flip-flops and combinational logics","author":"fuketa","year":"2011","journal-title":"Proc ISLPED"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2203834"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1594233.1594239"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/4.913744"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.7567\/JJAP.55.04ED06"},{"key":"ref15","year":"2017","journal-title":"Predictive Technology Model (PTM)"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2020594"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.873215"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1214\/aoms\/1177730951"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2014.6894413"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2011.6131609"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007164"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/4.871332"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024942"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1393921.1393952"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2009.2034233"},{"key":"ref2","first-page":"134","article-title":"An 80 nW retention 11.7pJ\/cycle active subthreshold ARM cortex-M0+ subsystem in 65 nm CMOS for WSN applications","author":"myers","year":"2015","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref1","first-page":"78","article-title":"An energy harvesting wireless sensor node for IoT systems featuring a near-threshold voltage IA-32 microcontroller in 14 nm tri-gate CMOS","author":"paul","year":"2016","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref9","first-page":"586","article-title":"24% power reduction by post-fabrication dual supply voltage control of 64 voltage domains in VDDmin limited ultra low voltage logic circuits","author":"yasufuku","year":"2012","journal-title":"Proc ISQED"},{"key":"ref20","first-page":"338","article-title":"A 77% energy-saving 22-transistor single-phase-clocking D-flip-flop with adaptive-coupling configuration in 40 nm CMOS","author":"teh","year":"2011","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.7567\/JJAP.54.04DC04"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7956364\/07882668.pdf?arnumber=7882668","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:59:59Z","timestamp":1642006799000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7882668\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,7]]},"references-count":21,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2017.2677978","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017,7]]}}}