{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,15]],"date-time":"2026-01-15T05:53:41Z","timestamp":1768456421110,"version":"3.49.0"},"reference-count":28,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2017,8,1]],"date-time":"2017-08-01T00:00:00Z","timestamp":1501545600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2017,8]]},"DOI":"10.1109\/tvlsi.2017.2688862","type":"journal-article","created":{"date-parts":[[2017,4,19]],"date-time":"2017-04-19T18:21:35Z","timestamp":1492626095000},"page":"2296-2306","source":"Crossref","is-referenced-by-count":13,"title":["High-Density 4T SRAM Bitcell in 14-nm 3-D CoolCube Technology Exploiting Assist Techniques"],"prefix":"10.1109","volume":"25","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-8986-8628","authenticated-orcid":false,"given":"Reda","family":"Boumchedda","sequence":"first","affiliation":[]},{"given":"Jean-Philippe","family":"Noel","sequence":"additional","affiliation":[]},{"given":"Bastien","family":"Giraud","sequence":"additional","affiliation":[]},{"given":"Kaya Can","family":"Akyel","sequence":"additional","affiliation":[]},{"given":"Melanie","family":"Brocard","sequence":"additional","affiliation":[]},{"given":"David","family":"Turgis","sequence":"additional","affiliation":[]},{"given":"Edith","family":"Beigne","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2015.7223698"},{"key":"ref11","first-page":"1","article-title":"Technology scaling: The CoolCube paradigm","author":"clermidy","year":"2015","journal-title":"Proc IEEE SOI-3D-Subthreshold Microelectron Technol Unified Conf"},{"key":"ref12","first-page":"191","article-title":"Robust multi-VT 4 T SRAM cell in 45 nm thin BOx fully-depleted SOI technology with ground plane","author":"noel","year":"2009","journal-title":"Proc IEEE Int Conf IC Design Technol"},{"key":"ref13","first-page":"457","article-title":"Energy-Efficient Cache Memories Using a Dual-$V_{t}$ 4T SRAM Cell with Read-Assist Techniques","author":"alireza shafaei","year":"2016","journal-title":"Design Automation Test in Europe Conference Exhibition (DATE)"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.1996.553582"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/CSICS.2014.6978554"},{"key":"ref16","first-page":"1","article-title":"High density SRAM bitcell architecture in 3D sequential CoolCube 14 nm technology","author":"brocard","year":"2016","journal-title":"Proc IEEE SOI-3D-Subthreshold Microelectron Technol Unified Conf"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ICETET.2011.23"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/IITC.2012.6251581"},{"key":"ref19","first-page":"195","article-title":"Compact 6 T SRAM cell with robust read\/write stabilizing design in 45 nm Monolithic 3D IC technology","author":"thomas","year":"2009","journal-title":"Proc IEEE Int Conf IC Design Technol"},{"key":"ref28","first-page":"191","article-title":"A 0.5 V VMIN 6 T SRAM in 28 nm UTBB FDSOI technology using compensated WLUD scheme with zero performance loss","author":"kumar","year":"2016","journal-title":"Proc 29th Int Conf VLSI Design 15th Int Conf Embedded Syst (VLSID)"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.50"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2015.2412973"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/INDICON.2015.7443263"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2013.6531994"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2002.1003727"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2009.92"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2013.6509680"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MCD.2005.1388765"},{"key":"ref9","first-page":"1","article-title":"First demonstration of a CMOS over CMOS 3D VLSI CoolCube integration on 300 mm wafers","author":"brunet","year":"2016","journal-title":"Proc VLSI Technol (VLSIT) Symp"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/5.371968"},{"key":"ref20","first-page":"137","article-title":"A simple and efficient concept for setting up multi-VT devices in thin BOx fully-depleted SOI technology","author":"noel","year":"2009","journal-title":"Proc Eur Solid State Device Res Conf"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2011.5938045"},{"key":"ref21","first-page":"415","article-title":"Circuit optimization of 4 T, 6 T, 8 T, 10 T SRAM bitcells in 28 nm UTBB FD-SOI technology using back-gate bias control","author":"asthana","year":"2013","journal-title":"Proc 32nd Eur Solid-State Device Research Conf (ESSDERC)"},{"key":"ref24","first-page":"160","article-title":"Impact of back bias on ultra-thin body and BOX (UTBB) devices","author":"liu","year":"2011","journal-title":"Proc Symp VLSI Technol (VLSIT)"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/DTIS.2013.6527801"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/CyberC.2015.32"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2109440"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7990278\/07904730.pdf?arnumber=7904730","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:03:14Z","timestamp":1642003394000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7904730\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,8]]},"references-count":28,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2017.2688862","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017,8]]}}}