{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T18:35:10Z","timestamp":1761676510486,"version":"3.37.3"},"reference-count":41,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2017,9,1]],"date-time":"2017-09-01T00:00:00Z","timestamp":1504224000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2017,9]]},"DOI":"10.1109\/tvlsi.2017.2707535","type":"journal-article","created":{"date-parts":[[2017,6,9]],"date-time":"2017-06-09T18:32:19Z","timestamp":1497033139000},"page":"2575-2587","source":"Crossref","is-referenced-by-count":4,"title":["Current-Mode Triline Transceiver for Coded Differential Signaling Across On-Chip Global Interconnects"],"prefix":"10.1109","volume":"25","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-4363-7303","authenticated-orcid":false,"given":"Nijwm","family":"Wary","sequence":"first","affiliation":[]},{"given":"Pradip","family":"Mandal","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","first-page":"262","article-title":"A 95fJ\/b current-mode transceiver for 10 mm on-chip interconnect","author":"lee","year":"2013","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/MWSYM.2013.6697762"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6176953"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.878112"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.892156"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2013.2261173"},{"key":"ref37","first-page":"180","article-title":"A source-synchronous 90Gb\/s capacitively driven serial on-chip link over 6 mm in 65nm CMOS","author":"walter","year":"2012","journal-title":"Proc IEEE Int Solid-State Circuits Conf"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.870922"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2006.357869"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.810060"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.837987"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.917547"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.904109"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2255070"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.893588"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2002682"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.897165"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2047458"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2336213"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2020859"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ACQED.2015.7274001"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2359665"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2011.2161394"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2559512"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2381637"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2009.2027634"},{"journal-title":"CMOS current-mode circuits for data communications","year":"2007","author":"yuan","key":"ref29"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2001949"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2012.6341301"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2005.1560205"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2036761"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.857351"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.910807"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cds.2014.0351"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.893661"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2185835"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2011038"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.859880"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.852010"},{"key":"ref26","first-page":"182","article-title":"A pin-efficient 20.83Gb\/s\/wire 0.94pJ\/bit forwarded clock CNRZ-5-coded SerDes up to 12 mm for MCM packages in 28nm CMOS","author":"shokrollahi","year":"2016","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757505"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8015212\/07945292.pdf?arnumber=7945292","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:04:30Z","timestamp":1642003470000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7945292\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,9]]},"references-count":41,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2017.2707535","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2017,9]]}}}