{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,20]],"date-time":"2026-02-20T07:07:21Z","timestamp":1771571241305,"version":"3.50.1"},"reference-count":49,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2017,9,1]],"date-time":"2017-09-01T00:00:00Z","timestamp":1504224000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"CENIIT at Link\u00f6ping University"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2017,9]]},"DOI":"10.1109\/tvlsi.2017.2710479","type":"journal-article","created":{"date-parts":[[2017,6,27]],"date-time":"2017-06-27T18:22:35Z","timestamp":1498587755000},"page":"2486-2497","source":"Crossref","is-referenced-by-count":26,"title":["Efficient FPGA Mapping of Pipeline SDF FFT Cores"],"prefix":"10.1109","volume":"25","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-9902-8825","authenticated-orcid":false,"given":"Carl","family":"Ingemarsson","sequence":"first","affiliation":[]},{"given":"Petter","family":"Kallstrom","sequence":"additional","affiliation":[]},{"given":"Fahad","family":"Qureshi","sequence":"additional","affiliation":[]},{"given":"Oscar","family":"Gustafsson","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1995.521402"},{"key":"ref38","year":"2008","journal-title":"XtremeDSP for Virtex-4 FPGAs User Guide"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2178275"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2013.6645545"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/2159542.2159547"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt.2010.0052"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2012.6339243"},{"key":"ref36","first-page":"1","article-title":"Area and frequency optimized 1024 point Radix-2 FFT processor on FPGA","author":"kumar","year":"2015","journal-title":"Proc Int Conf VLSI Syst Archit Technol Appl (VLSI-SATA)"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/ISICIR.2014.7029571"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TII.2012.2220371"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/iCECE.2010.1114"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ICCNT.2010.12"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2011.6026390"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.884574"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2015.2392104"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1049\/el:20030892"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2005.1465885"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2004.1339538"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCE.2009.5174479"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TAES.2008.4667732"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1155\/2009\/219140"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2009.5413113"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2008.2008074"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1631\/jzus.C1000234"},{"key":"ref40","year":"2008","journal-title":"Virtex-4 FPGA User Guide (UG070)"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2319335"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2016.2538119"},{"key":"ref14","first-page":"766","article-title":"A new approach to pipeline FFT processor","author":"he","year":"1996","journal-title":"Proc Int Conf Parallel Process"},{"key":"ref15","first-page":"257","article-title":"Designing pipeline FFT processor for OFDM (de)modulation","author":"he","year":"1998","journal-title":"Proc URSI Int Symp Signals Syst Electron"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TSP.2009.2016276"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2006.888764"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ECCTD.2011.6043634"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2304664"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1984.1676458"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1975482.1975484"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TAU.1973.1162428"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1970.222826"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/29.45545"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1974.223800"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1016\/B978-012734530-7\/50001-5"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2006.875306"},{"key":"ref46","year":"2009","journal-title":"Virtex-4 FPGA Data Sheet DC and Switching Characteristics"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2011.2164144"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/LSP.2002.803408"},{"key":"ref47","year":"2014","journal-title":"Virtex-4 FPGA Data Sheet DC and Switching Characteristics"},{"key":"ref42","year":"2011","journal-title":"Virtex-6 FPGA DSP48E1 Slice User Guide"},{"key":"ref41","year":"2012","journal-title":"Configurable Logic Blocks (CLBs) in Virtex-5 FPGA User Guide"},{"key":"ref44","year":"2015","journal-title":"UltraScale Achitecture DSP Slice User Guide (UG579)"},{"key":"ref43","year":"2009","journal-title":"Spartan-6 FPGA DSP48A1 Slice User Guide"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8015212\/07959623.pdf?arnumber=7959623","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:04:30Z","timestamp":1642003470000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7959623\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,9]]},"references-count":49,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2017.2710479","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017,9]]}}}