{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,20]],"date-time":"2025-06-20T04:10:42Z","timestamp":1750392642125,"version":"3.41.0"},"reference-count":21,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2017,9,1]],"date-time":"2017-09-01T00:00:00Z","timestamp":1504224000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2017,9,1]],"date-time":"2017-09-01T00:00:00Z","timestamp":1504224000000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2017,9,1]],"date-time":"2017-09-01T00:00:00Z","timestamp":1504224000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2017,9,1]],"date-time":"2017-09-01T00:00:00Z","timestamp":1504224000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000001","name":"NSF","doi-asserted-by":"publisher","award":["CCF-1217076"],"award-info":[{"award-number":["CCF-1217076"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2017,9]]},"DOI":"10.1109\/tvlsi.2017.2712804","type":"journal-article","created":{"date-parts":[[2017,6,23]],"date-time":"2017-06-23T18:47:22Z","timestamp":1498243642000},"page":"2616-2624","source":"Crossref","is-referenced-by-count":1,"title":["Using a Device State Library to Boost the Performance of TCAD Mixed-Mode Simulation"],"prefix":"10.1109","volume":"25","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-3098-2714","authenticated-orcid":false,"given":"Xiaoliang","family":"Dai","sequence":"first","affiliation":[]},{"given":"Niraj K.","family":"Jha","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2013.6658493"},{"key":"ref11","first-page":"1","article-title":"New simulation method for deep trench termination diode (DT2) using mixed-mode TCAD Sentaurus","author":"baccar","year":"2015","journal-title":"Proc Int Conf Thermal Mech Multi-Phys Simulation Experim Microelectron Microsyst"},{"key":"ref12","first-page":"41","article-title":"Robustness evaluation of ESD protection devices in NEMS using a novel TCAD methodology","author":"cui","year":"2008","journal-title":"Proc IEEE Int Conf Nano\/Micro Eng Molecular Syst"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRev.126.2002"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1016\/j.cpc.2010.07.018"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1137\/S0036139992240425"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2005.857184"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/43.149771"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/43.3217"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1016\/S0026-2692(00)00083-5"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevLett.93.196805"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2012.6330657"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2016.34"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1016\/0899-8248(91)90004-E"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2564300"},{"journal-title":"Sentaurus TCAD Tool Suite","year":"2016","key":"ref7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1155\/2014\/365689"},{"journal-title":"ATLAS Users Manual","year":"2016","key":"ref9"},{"key":"ref1","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-031-01690-5","author":"vasileska","year":"2006","journal-title":"Computational Electronics"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2008.4588544"},{"key":"ref21","first-page":"16","article-title":"Modeling of width-quantization-induced variations in logic FinFETs for 22 nm and beyond","author":"lin","year":"2011","journal-title":"Proc Symp VLSI Technol"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/ieeexplore.ieee.org\/ielaam\/92\/8015212\/7956201-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8015212\/07956201.pdf?arnumber=7956201","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,20]],"date-time":"2025-06-20T00:07:09Z","timestamp":1750378029000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7956201\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,9]]},"references-count":21,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2017.2712804","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2017,9]]}}}