{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,6]],"date-time":"2026-01-06T13:09:53Z","timestamp":1767704993671,"version":"3.37.3"},"reference-count":33,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2017,11,1]],"date-time":"2017-11-01T00:00:00Z","timestamp":1509494400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2017,11]]},"DOI":"10.1109\/tvlsi.2017.2729587","type":"journal-article","created":{"date-parts":[[2017,8,1]],"date-time":"2017-08-01T18:33:25Z","timestamp":1501612405000},"page":"3045-3056","source":"Crossref","is-referenced-by-count":12,"title":["Logic Design Partitioning for Stacked Power Domains"],"prefix":"10.1109","volume":"25","author":[{"given":"Kristof","family":"Blutman","sequence":"first","affiliation":[]},{"given":"Hamed","family":"Fatemi","sequence":"additional","affiliation":[]},{"given":"Ajay","family":"Kapoor","sequence":"additional","affiliation":[]},{"given":"Andrew B.","family":"Kahng","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3420-9764","authenticated-orcid":false,"given":"Jiajia","family":"Li","sequence":"additional","affiliation":[]},{"given":"Jose","family":"Pineda de Gyvez","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"Design Compiler User’s Manual","year":"2013","key":"ref33"},{"year":"2015","key":"ref32"},{"journal-title":"Cadence Innovus User Guide","year":"2016","key":"ref31"},{"journal-title":"Hungarian algorithm","year":"2016","key":"ref30"},{"key":"ref10","first-page":"194","article-title":"VLSI circuit partitioning by cluster-removal using iterative improvement techniques","author":"dutt","year":"1996","journal-title":"Proc ICCAD"},{"key":"ref11","first-page":"175","article-title":"A linear time heuristic for improving network partitions","author":"fiduccia","year":"1982","journal-title":"Proc DAC"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/227683.227684"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2007.358063"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/43.662682"},{"key":"ref15","first-page":"885","article-title":"Methodology from chaos in IC implementation","author":"jeong","year":"2010","journal-title":"Proc ISQED"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/640000.640019"},{"key":"ref17","first-page":"343","article-title":"Multilevel K-way hypergraph partitioning","author":"karypis","year":"1999","journal-title":"Proc DAC"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1137\/S1064827595287997"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1002\/j.1538-7305.1970.tb01770.x"},{"key":"ref28","first-page":"309","article-title":"Post-placement voltage island generation under performance requirement","author":"wu","year":"2005","journal-title":"Proc ICCAD"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2016.7573478"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2274829"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898041"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/368434.368864"},{"key":"ref29","first-page":"1533","article-title":"Efficient network flow based min-cut balanced partitioning","volume":"15","author":"yang","year":"1996","journal-title":"IEEE Trans Comput -Aided Des Integr Circuits Syst"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837451"},{"key":"ref8","first-page":"641","article-title":"Post-placement voltage Island generation","author":"ching","year":"2006","journal-title":"Proc ICCAD"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/43.892854"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2017.7858363"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/217474.217536"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1016\/0167-9260(95)00008-4"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1984.1676460"},{"key":"ref22","first-page":"400","article-title":"A 0.1 pJ\/b 5-to-10 Gb\/s charge-recycling stacked low-power I\/O for on-chip signaling in 45 nm CMOS SOI","author":"liu","year":"2013","journal-title":"Proc ISSCC"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2015.7231306"},{"key":"ref24","first-page":"298","article-title":"High-tension power delivery: Operating \n$0.18~\\mu$\nm CMOS digital logic at 5.4 V","author":"rajapandian","year":"2005","journal-title":"Proc ISSCC"},{"journal-title":"DCDC Performance Survey","year":"2017","author":"steyaert","key":"ref23"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/157485.165121"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/43.476579"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8079089\/07999260.pdf?arnumber=7999260","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:22:21Z","timestamp":1642004541000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7999260\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,11]]},"references-count":33,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2017.2729587","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2017,11]]}}}