{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:21:50Z","timestamp":1740133310334,"version":"3.37.3"},"reference-count":46,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2017,11,1]],"date-time":"2017-11-01T00:00:00Z","timestamp":1509494400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2017,11,1]],"date-time":"2017-11-01T00:00:00Z","timestamp":1509494400000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2017,11,1]],"date-time":"2017-11-01T00:00:00Z","timestamp":1509494400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2017,11,1]],"date-time":"2017-11-01T00:00:00Z","timestamp":1509494400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation CAREER Award","doi-asserted-by":"publisher","award":["CCF-1350451"],"award-info":[{"award-number":["CCF-1350451"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"National Science Foundation Award","doi-asserted-by":"publisher","award":["CCF-1421988"],"award-info":[{"award-number":["CCF-1421988"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100004351","name":"Cisco Research Award","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100004351","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2017,11]]},"DOI":"10.1109\/tvlsi.2017.2742944","type":"journal-article","created":{"date-parts":[[2017,9,4]],"date-time":"2017-09-04T18:08:20Z","timestamp":1504548500000},"page":"3019-3032","source":"Crossref","is-referenced-by-count":13,"title":["Efficiency, Stability, and Reliability Implications of Unbalanced Current Sharing Among Distributed On-Chip Voltage Regulators"],"prefix":"10.1109","volume":"25","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-1836-3614","authenticated-orcid":false,"given":"Longfei","family":"Wang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S. Karen","family":"Khatamifard","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Orhun Aras","family":"Uzun","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ulya R.","family":"Karpuzcu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Selcuk","family":"Kose","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056064"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/T-ED.1969.16754"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593180"},{"article-title":"DC–DC converters—Dynamic model design and experimental verification","year":"2004","author":"johansson","key":"ref31"},{"journal-title":"Switch-Mode Power Supplies SPICE Simulations and Practical Designs","year":"2008","author":"basso","key":"ref30"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1007\/s10470-009-9365-z"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4899-1331-9"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2501353"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2012.2226378"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1145\/2063384.2063454"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2190539"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1785481.1785568"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2555954"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2396998"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TPEL.2009.2037892"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/PESC.2006.1712203"},{"key":"ref17","first-page":"96","article-title":"POWER8: A 12-core server-class processor in 22 nm SOI with 7.6 Tb\/s off-chip bandwidth","author":"fluhr","year":"2014","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2014.6853199"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2011.09.003"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/PESC.1976.7072895"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2012.2215392"},{"key":"ref27","first-page":"432","article-title":"FIVR—Fully integrated voltage regulators on 4th generation Intel Core SoCs","author":"burton","year":"2014","journal-title":"Proc IEEE APEC"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2274826"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2185354"},{"article-title":"Dynamical profile of switched-mode converter—Fact or fiction?","year":"2007","author":"hankaniemi","key":"ref29"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2014.2315880"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2256393"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TPEL.2015.2493512"},{"journal-title":"Computer Architecture A Quantitative Approach","year":"2011","author":"hennessy","key":"ref2"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-29395-0"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837483"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2015.7273506"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2011.2168016"},{"journal-title":"Printed Circuit Board (PCB) Power Delivery Network (PDN) Design Methodology","year":"2016","key":"ref45"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TPEL.2007.904237"},{"key":"ref21","first-page":"247","article-title":"A 45 nm logic technology with high-k+metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pb-free packaging","author":"mistry","year":"2007","journal-title":"IEDM Tech Dig"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1145\/980152.980157"},{"key":"ref24","first-page":"612","article-title":"Optimizing design for low voltage DC–DC converters","author":"zhou","year":"1997","journal-title":"Proc IEEE APEC"},{"key":"ref41","first-page":"1","article-title":"HotLeakage: A temperature-aware model of subthreshold and gate leakage for architects","author":"zhang","year":"2003"},{"journal-title":"TI Application Report SLVA079","year":"1999","key":"ref23"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593243"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/pesc.2006.1712202"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2014.6742946"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/APASIC.2002.1031555"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/ieeexplore.ieee.org\/ielaam\/92\/8079089\/8025419-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8079089\/08025419.pdf?arnumber=8025419","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,8]],"date-time":"2022-04-08T18:48:32Z","timestamp":1649443712000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8025419\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,11]]},"references-count":46,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2017.2742944","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2017,11]]}}}