{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:21:51Z","timestamp":1740133311782,"version":"3.37.3"},"reference-count":35,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2018,1,1]],"date-time":"2018-01-01T00:00:00Z","timestamp":1514764800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2018,1,1]],"date-time":"2018-01-01T00:00:00Z","timestamp":1514764800000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2018,1,1]],"date-time":"2018-01-01T00:00:00Z","timestamp":1514764800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2018,1,1]],"date-time":"2018-01-01T00:00:00Z","timestamp":1514764800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CNS-0953447"],"award-info":[{"award-number":["CNS-0953447"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2018,1]]},"DOI":"10.1109\/tvlsi.2017.2757477","type":"journal-article","created":{"date-parts":[[2017,10,13]],"date-time":"2017-10-13T18:38:58Z","timestamp":1507919938000},"page":"110-121","source":"Crossref","is-referenced-by-count":6,"title":["&lt;italic&gt;PhLock:&lt;\/italic&gt; A Cache Energy Saving Technique Using Phase-Based Cache Locking"],"prefix":"10.1109","volume":"26","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-2800-4834","authenticated-orcid":false,"given":"Tosiron","family":"Adegbija","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ann","family":"Gordon-Ross","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1002\/bltj.21532"},{"key":"ref32","doi-asserted-by":"crossref","first-page":"336","DOI":"10.1145\/871656.859657","article-title":"Phase tracking and prediction","volume":"31","author":"sherwood","year":"2003","journal-title":"ACM SIGARCH Comput Archit News"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2003.1261391"},{"key":"ref30","doi-asserted-by":"crossref","first-page":"165","DOI":"10.1145\/1037949.1024414","article-title":"Locality phase prediction","volume":"39","author":"shen","year":"2004","journal-title":"ACM SIGOPS Operating Syst Rev"},{"key":"ref35","doi-asserted-by":"crossref","first-page":"4","DOI":"10.1145\/1324969.1324973","article-title":"Data cache locking for tight timing calculations","volume":"7","author":"vera","year":"2007","journal-title":"ACM Trans Embedded Comput Syst"},{"key":"ref34","doi-asserted-by":"crossref","first-page":"272","DOI":"10.1145\/885651.781062","article-title":"Data cache locking for higher program predictability","volume":"31","author":"vera","year":"2003","journal-title":"ACM SIGMETRICS Perform Eval Rev"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/268806.268810"},{"journal-title":"Synopsys","year":"2001","key":"ref11"},{"key":"ref12","first-page":"27","article-title":"WCET-Centric dynamic instruction cache locking","author":"ding","year":"2014","journal-title":"Proc Design Automation Test Eur Conf Exhib"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1289816.1289853"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/WWC.2001.990739"},{"key":"ref15","first-page":"1","article-title":"SIMPOINT 3.0: Faster and more flexible program phase analysis","volume":"7","author":"hamerly","year":"2005","journal-title":"Instruction-Level Parallelism"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837362"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2418320"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1007\/s11241-011-9139-4"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/SECON.2015.7133037"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2012.6164950"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2013.6657066"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/REAL.2002.1181567"},{"journal-title":"SPEC CPU2006","year":"2016","key":"ref3"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2700100"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/2638557"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1629395.1629422"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2010.02.002"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/AICCSA.2009.5069404"},{"journal-title":"MIPS32 M14K","year":"2017","key":"ref2"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/360128.360153"},{"journal-title":"ARM","year":"2016","key":"ref1"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.37"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1016\/j.suscom.2013.11.001"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/344166.344610"},{"key":"ref24","first-page":"22","article-title":"Cacti 6.0: A tool to model large caches","author":"muralimanohar","year":"2009"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/2858792"},{"key":"ref26","first-page":"1","article-title":"Dynamic instruction cache locking in hard real-time systems","author":"puaut","year":"2006","journal-title":"Proc Int Conf Real-Time Netw Syst"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1371\/journal.pone.0082975"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/ieeexplore.ieee.org\/ielaam\/92\/8240812\/8067445-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8240812\/08067445.pdf?arnumber=8067445","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,8]],"date-time":"2022-04-08T18:48:30Z","timestamp":1649443710000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8067445\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,1]]},"references-count":35,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2017.2757477","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2018,1]]}}}