{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,10]],"date-time":"2026-07-10T20:32:09Z","timestamp":1783715529824,"version":"3.55.0"},"reference-count":44,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2018,1,1]],"date-time":"2018-01-01T00:00:00Z","timestamp":1514764800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100004663","name":"Ministry of Science and Technology of Taiwan","doi-asserted-by":"publisher","award":["MOST 105-2221-E-006-241"],"award-info":[{"award-number":["MOST 105-2221-E-006-241"]}],"id":[{"id":"10.13039\/501100004663","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100004663","name":"Ministry of Science and Technology of Taiwan","doi-asserted-by":"publisher","award":["106-2221-E-006-027-MY3"],"award-info":[{"award-number":["106-2221-E-006-027-MY3"]}],"id":[{"id":"10.13039\/501100004663","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2018,1]]},"DOI":"10.1109\/tvlsi.2017.2764520","type":"journal-article","created":{"date-parts":[[2017,11,10]],"date-time":"2017-11-10T19:20:00Z","timestamp":1510341600000},"page":"50-62","source":"Crossref","is-referenced-by-count":11,"title":["Mitigating BTI-Induced Degradation in STT-MRAM Sensing Schemes"],"prefix":"10.1109","volume":"26","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1994-7512","authenticated-orcid":false,"given":"Ing-Chao","family":"Lin","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yun Kae","family":"Law","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2093-1788","authenticated-orcid":false,"given":"Yuan","family":"Xie","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2012.6187506"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2010.5537129"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2014.7001394"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2012.6241840"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147172"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2013.2238237"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/1065010.1065034"},{"key":"ref36","author":"fong","year":"2014","journal-title":"Purdue Nanoelectronics Research Laboratory Magnetic Tunnel Junction Model 1 0 0"},{"key":"ref35","author":"cao","year":"2012","journal-title":"Predictive Technology Model (PTM)"},{"key":"ref34","first-page":"136","article-title":"Energy- and endurance-aware design of phase change memory caches","author":"joo","year":"2010","journal-title":"Proc Design Autom Test Eur Conf Exhib"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.884870"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/NANOARCH.2015.7180576"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2016.7573371"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2016.7573373"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2339364"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2015.7116291"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/IDT.2013.6727094"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2012.6187515"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.30"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2278549"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2006.73"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2012.6479023"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2011.5993623"},{"key":"ref27","first-page":"24.1.1","article-title":"Extended scalability of perpendicular STT-MRAM towards sub-20 nm MTJ node","author":"kim","year":"2011","journal-title":"IEDM Tech Dig"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2011.20"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1063\/1.369932"},{"key":"ref29","first-page":"45","article-title":"Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design","author":"chen","year":"2012","journal-title":"Proc Design Autom Test Eur Conf Exhib"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2463585.2463589"},{"key":"ref8","first-page":"112507-1","article-title":"Switching current reduction using perpendicular anisotropy in CoFeB&#x2013;MgO magnetic tunnel junctions","volume":"98","author":"amiri","year":"2011","journal-title":"Appl Phys Lett"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2016.2521712"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2003.1250885"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2011.6105369"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2000.155259"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2010.5450504"},{"key":"ref22","first-page":"163","article-title":"Impacts of NBTI\/PBTI on SRAM VMIN and design techniques for SRAM VMIN improvement","author":"kim","year":"2011","journal-title":"Proc Int SoC Design Conf"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2011.2158708"},{"key":"ref42","year":"2016","journal-title":"Synopsys Design Compiler"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2088143"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2009.2024325"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2010.15"},{"key":"ref44","author":"dong","year":"2012","journal-title":"NVSim A Circuit-level Performance Energy and Area Model for Emerging Nonvolatile Memory"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1063\/1.3694270"},{"key":"ref43","author":"stillmaker","year":"2011","journal-title":"Toward more accurate scaling estimates of CMOS circuits from 180 nm to 22 nm &#x201D;"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-15180-9_1"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8240812\/08103882.pdf?arnumber=8103882","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:24:44Z","timestamp":1642004684000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8103882\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,1]]},"references-count":44,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2017.2764520","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,1]]}}}