{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:21:52Z","timestamp":1740133312541,"version":"3.37.3"},"reference-count":52,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2018,3,1]],"date-time":"2018-03-01T00:00:00Z","timestamp":1519862400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2018,3]]},"DOI":"10.1109\/tvlsi.2017.2767543","type":"journal-article","created":{"date-parts":[[2017,11,7]],"date-time":"2017-11-07T19:10:45Z","timestamp":1510081845000},"page":"457-469","source":"Crossref","is-referenced-by-count":4,"title":["Fine-Grained Energy-Constrained Microprocessor Pipeline Design"],"prefix":"10.1109","volume":"26","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-8408-5691","authenticated-orcid":false,"given":"Anteneh","family":"Gebregiorgis","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mehdi B.","family":"Tahoori","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2002.1010651"},{"article-title":"Contention-free level converting flip-flops for low-swing clocking","year":"2015","author":"zlatanovici","key":"ref38"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2020201"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2002.1176261"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/545214.545217"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2282316"},{"key":"ref37","first-page":"407","article-title":"Self&#x2013;precharging flip&#x2013;flop (SPFF): A new level converting flip-flop","author":"mahmoodi-meimand","year":"2002","journal-title":"Proc 28th Eur Solid-State Circuits Conf"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2002426"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2014.04.035"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2011972"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.852162"},{"article-title":"Simplified multi-threshold voltage scheme for fully depleted soi mosfets","year":"2015","author":"cheng","key":"ref27"},{"key":"ref29","first-page":"825","article-title":"Slack redistribution for graceful degradation under voltage overscaling","author":"kahng","year":"2010","journal-title":"Proc Asia South Pacific Design Autom Conf"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2011.2177004"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1016\/j.mee.2009.03.129"},{"key":"ref20","first-page":"64","article-title":"Minimum energy tracking loop with embedded DC&#x2013;DC converter delivering voltages down to 250 mV in 65 nm CMOS","author":"ramadass","year":"2007","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref22","first-page":"868","article-title":"Theoretical and practical limits of dynamic voltage scaling","author":"bo zhai","year":"2004","journal-title":"Proceedings 41st Design Automation Conference 2004 DAC"},{"key":"ref21","doi-asserted-by":"crossref","first-page":"90","DOI":"10.1145\/1013235.1013265","article-title":"Characterizing and Modeling Minimum Energy Operation for Subthreshold Circuits","author":"calhoun","year":"2004","journal-title":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design LPE"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1093\/ietele\/e88-c.4.509"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2002.1016866"},{"key":"ref26","doi-asserted-by":"crossref","first-page":"278","DOI":"10.1145\/1016568.1016641","article-title":"Low power gate-level design with mixed-Vth\/(MVT) techniques","author":"sill","year":"2004","journal-title":"Proc 17th Symp Integr Circuits Syst Design"},{"key":"ref25","article-title":"Low-power design using multiple VT H ASIC libraries","author":"buurma","year":"2004","journal-title":"SOC Central"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.870912"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6177103"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/TSP.2016.2546224"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2934583.2934635"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2980081"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1145\/871506.871535"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2035060"},{"key":"ref13","first-page":"1149","article-title":"Near-threshold voltage (NTV) design&#x2014;Opportunities and challenges","author":"kaul","year":"2012","journal-title":"Proc 49th ACM\/EDAC\/IEEE Design Autom Conf"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2034764"},{"key":"ref15","first-page":"1801","article-title":"Realization of ultra low voltage circuit design for Internet of Things","volume":"21","author":"kumar","year":"2015","journal-title":"Electron Devices"},{"key":"ref16","doi-asserted-by":"crossref","DOI":"10.1145\/2821510","article-title":"A survey of architectural techniques for near-threshold computing","volume":"12","author":"mittal","year":"2016","journal-title":"ACM J Emerg Technol Comput Syst"},{"key":"ref17","first-page":"205","article-title":"A Cross-Layer Analysis of Soft Error, Aging and Process Variation in Near Threshold Computing","author":"anteneh gebregiorgis","year":"2016","journal-title":"Design Automation Test in Europe Conference Exhibition (DATE)"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/1283780.1283789"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2035453"},{"journal-title":"Dynamic Power Management Design Techniques and CAD Tools","year":"2012","author":"benini","key":"ref4"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2014.73"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2015.7169143"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2012.6164978"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1201\/b14072-7"},{"key":"ref7","first-page":"84","article-title":"Energy-harvesting wireless sensor networks","author":"fafoutis","year":"2012","journal-title":"Proc 9th Eur Conf Wireless Sensor Netw"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007145"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1002\/9781118511305.ch20"},{"journal-title":"Cadence-Incisive A Unified Simulation Engine","year":"2016","key":"ref46"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/2.869367"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1147\/rd.504.0469"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1145\/1840845.1840934"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2007.358087"},{"key":"ref41","first-page":"195","article-title":"Managing power and performance for system-on-chip designs using voltage islands","author":"lackey","year":"2002","journal-title":"Proc Int Conf Comput -Aided Design"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2012.23"},{"journal-title":"OpenSPARC T1","year":"2016","key":"ref43"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8300457\/08100633.pdf?arnumber=8100633","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,8,6]],"date-time":"2022-08-06T17:54:20Z","timestamp":1659808460000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8100633\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,3]]},"references-count":52,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2017.2767543","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2018,3]]}}}