{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,10]],"date-time":"2025-12-10T08:44:41Z","timestamp":1765356281403,"version":"3.37.3"},"reference-count":18,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2018,3,1]],"date-time":"2018-03-01T00:00:00Z","timestamp":1519862400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100003621","name":"Institute for Information and communications Technology Promotion (IITP)","doi-asserted-by":"publisher","award":["IITP-2017-2012-0-00641"],"award-info":[{"award-number":["IITP-2017-2012-0-00641"]}],"id":[{"id":"10.13039\/501100003621","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2018,3]]},"DOI":"10.1109\/tvlsi.2017.2773642","type":"journal-article","created":{"date-parts":[[2017,12,8]],"date-time":"2017-12-08T20:45:57Z","timestamp":1512765957000},"page":"522-530","source":"Crossref","is-referenced-by-count":4,"title":["A 12.5-Gb\/s Near-Ground Transceiver Employing a MaxEye Algorithm-Based Adaptation Technique"],"prefix":"10.1109","volume":"26","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-7012-9991","authenticated-orcid":false,"given":"Jahoon","family":"Jin","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1766-6848","authenticated-orcid":false,"given":"Seok","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Xuefan","family":"Jin","sequence":"additional","affiliation":[]},{"given":"Sang-Hoon","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Jung-Hoon","family":"Chun","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2006.1696052"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2006.881161"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2014.2361718"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.831600"},{"key":"ref14","first-page":"436","article-title":"A 12.5 Gb\/s SerDes in 65 nm CMOS using a baud-rate ADC with digital receiver equalization and clock recovery","author":"harwood","year":"2007","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2031021"},{"key":"ref16","first-page":"350","article-title":"Analog-DFE-based 16 Gb\/s SerDes in 40 nm CMOS that operates across 34 dB loss channels at Nyquist with a baud rate CDR and 1.2 Vpp voltage-mode driver","author":"joy","year":"2011","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2014.2350294"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2705070"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2013.2262186"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.825259"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2014.6865428"},{"key":"ref5","first-page":"132","article-title":"A 0.4 mW\/Gb\/s 16Gb\/s near-ground receiver front-end with replica transconductance termination calibration","author":"kaviani","year":"2012","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2001871"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.1986.1168755"},{"key":"ref2","first-page":"25","article-title":"A 16 Gb\/s 65 nm CMOS transceiver for a memory interface","author":"chun","year":"2008","journal-title":"Proc IEEE Asian Solid-State Circuits Conf"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908692"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.842863"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8300457\/08171210.pdf?arnumber=8171210","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:21:54Z","timestamp":1642004514000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8171210\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,3]]},"references-count":18,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2017.2773642","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2018,3]]}}}