{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,30]],"date-time":"2026-04-30T17:09:04Z","timestamp":1777568944753,"version":"3.51.4"},"reference-count":29,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2018,3,1]],"date-time":"2018-03-01T00:00:00Z","timestamp":1519862400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2018,3,1]],"date-time":"2018-03-01T00:00:00Z","timestamp":1519862400000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2018,3,1]],"date-time":"2018-03-01T00:00:00Z","timestamp":1519862400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2018,3,1]],"date-time":"2018-03-01T00:00:00Z","timestamp":1519862400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"NSFC","doi-asserted-by":"publisher","award":["61401008"],"award-info":[{"award-number":["61401008"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100002367","name":"State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences","doi-asserted-by":"publisher","award":["CARCH201602"],"award-info":[{"award-number":["CARCH201602"]}],"id":[{"id":"10.13039\/501100002367","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100005144","name":"Qualcomm gift","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100005144","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"NSF","doi-asserted-by":"publisher","award":["1533933"],"award-info":[{"award-number":["1533933"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"NSF","doi-asserted-by":"publisher","award":["1461698"],"award-info":[{"award-number":["1461698"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"NSF","doi-asserted-by":"publisher","award":["1500848"],"award-info":[{"award-number":["1500848"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"NSF","doi-asserted-by":"publisher","award":["1719160"],"award-info":[{"award-number":["1719160"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2018,3]]},"DOI":"10.1109\/tvlsi.2017.2780522","type":"journal-article","created":{"date-parts":[[2018,1,5]],"date-time":"2018-01-05T19:52:49Z","timestamp":1515181969000},"page":"484-495","source":"Crossref","is-referenced-by-count":22,"title":["An Adaptive 3T-3MTJ Memory Cell Design for STT-MRAM-Based LLCs"],"prefix":"10.1109","volume":"26","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-6688-1790","authenticated-orcid":false,"given":"Linuo","family":"Xue","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9972-0478","authenticated-orcid":false,"given":"Bi","family":"Wu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Beibei","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2477-314X","authenticated-orcid":false,"given":"Yuanqing","family":"Cheng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Peiyuan","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9696-1129","authenticated-orcid":false,"given":"Chando","family":"Park","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2480-6776","authenticated-orcid":false,"given":"Jimmy","family":"Kan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Seung H.","family":"Kang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuan","family":"Xie","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","year":"0","journal-title":"Interconnect Models"},{"key":"ref11","first-page":"1","article-title":"45nm low power CMOS logic compatible embedded STT-MRAM utilizing a reverse-connection 1T\/1MTJ cell","author":"lin","year":"2009","journal-title":"IEDM Tech Dig"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2009.5424242"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2013.6582102"},{"key":"ref14","first-page":"46","article-title":"1 Mb 4 T-2 MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns\/200ps wake-up\/power-off times","author":"ohsawa","year":"2012","journal-title":"Proc IEEE Symp VLSI Circuits (VLSIC)"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2088143"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2009.2024325"},{"key":"ref17","first-page":"54","article-title":"STTRAM scaling and retention failure","volume":"17","author":"naeimi","year":"2013","journal-title":"Intel Technol J"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2014.6858403"},{"key":"ref19","first-page":"1","article-title":"Leveraging systematic unidirectional error-detecting codes for fast STT-MRAM cache","author":"nour sayed","year":"2017","journal-title":"Proc IEEE VLSI Test Symp (VTS)"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2015.2412960"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2015.7062962"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/NANO.2013.6720849"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1038\/nmat2804"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2013.6724690"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2016.2601330"},{"key":"ref5","first-page":"224","article-title":"Cycling endurance optimization scheme for 1Mb STT-MRAM in 40nm technology","author":"yu","year":"2013","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref8","first-page":"108c","article-title":"A 250-MHz 256b-I\/O 1-Mb STT-MRAM with advanced perpendicular MTJ based dual cell for nonvolatile magnetic caches to reduce active power of rocessors","author":"noguchi","year":"2013","journal-title":"Proc IEEE Symp VLSI Circuits (VLSIC)"},{"key":"ref7","first-page":"24.1.1","article-title":"Extended scalability of perpendicular STT-MRAM towards sub-20nm MTJ node","author":"kim","year":"2011","journal-title":"IEDM Tech Dig"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2013.6557176"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2015.7409770"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2032192"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870428"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1088\/0022-3727\/45\/29\/295002"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2185930"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/1241601.1241618"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/2463585.2463589"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429498"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/ieeexplore.ieee.org\/ielaam\/92\/8300457\/8247255-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8300457\/08247255.pdf?arnumber=8247255","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,8]],"date-time":"2022-04-08T18:48:34Z","timestamp":1649443714000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8247255\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,3]]},"references-count":29,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2017.2780522","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,3]]}}}