{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:21:57Z","timestamp":1740133317662,"version":"3.37.3"},"reference-count":61,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2018,7,1]],"date-time":"2018-07-01T00:00:00Z","timestamp":1530403200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2018,7,1]],"date-time":"2018-07-01T00:00:00Z","timestamp":1530403200000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2018,7,1]],"date-time":"2018-07-01T00:00:00Z","timestamp":1530403200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2018,7,1]],"date-time":"2018-07-01T00:00:00Z","timestamp":1530403200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CCF-1514780","CNS-1628961"],"award-info":[{"award-number":["CCF-1514780","CNS-1628961"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2018,7]]},"DOI":"10.1109\/tvlsi.2018.2809961","type":"journal-article","created":{"date-parts":[[2018,3,29]],"date-time":"2018-03-29T18:06:05Z","timestamp":1522346765000},"page":"1277-1289","source":"Crossref","is-referenced-by-count":2,"title":["A Novel Hybrid Delay Unit Based on Dummy TSVs for 3-D On-Chip Memory"],"prefix":"10.1109","volume":"26","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-2408-1488","authenticated-orcid":false,"given":"Xiaowei","family":"Chen","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5045-9720","authenticated-orcid":false,"given":"Seyed Alireza","family":"Pourbakhsh","sequence":"additional","affiliation":[]},{"given":"Jingyan","family":"Fu","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3297-7436","authenticated-orcid":false,"given":"Na","family":"Gong","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4731-8481","authenticated-orcid":false,"given":"Jinhui","family":"Wang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"Interconnect Scaling Trends","year":"2017","key":"ref39"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2010.73"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ICEAC.2010.5702291"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2289964"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1147\/rd.504.0491"},{"key":"ref30","first-page":"580","article-title":"Dummy TSV based bit-line optimization in 3D on-chip memory","author":"chen","year":"2016","journal-title":"Proc IEEE Int Conf Electr \/Inf Technol"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2013.2239362"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2009.2034508"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2010.5654245"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2012.6187499"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1109\/SMARTSENS.2015.7873605"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2390214"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2013.6509681"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2014.2379645"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2270285"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2010.50"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2334136"},{"key":"ref20","first-page":"117","author":"qian","year":"2012","journal-title":"Solid and Structural Analysis With the Finite Element Method"},{"journal-title":"FreePDK45","year":"2017","key":"ref22"},{"journal-title":"7HV CMOS Process","year":"2017","key":"ref21"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2011.2120607"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2015.7085479"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2354347"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2010.2099590"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2010.5653753"},{"journal-title":"Graphics Processing Units (GPUs) Architecture and Programming","year":"2017","author":"zahran","key":"ref51"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1109\/ICRITO.2014.7014674"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1109\/ICECE.2012.6471650"},{"key":"ref57","first-page":"61","article-title":"A 12 ps true-time-delay phase shifter with 6.6% delay variation at 20–40 GHz","author":"ma","year":"2013","journal-title":"Proc IEEE Radio Freq Integr Circuits Symp (RFIC)"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1109\/ICICDT.2014.6838582"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2009.4796507"},{"key":"ref54","first-page":"300","article-title":"TSV-aware topology generation for 3D clock tree synthesis","author":"liu","year":"2013","journal-title":"Proc Int Symp Quality Electron Design (ISQED)"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1629928"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2017.7918314"},{"key":"ref10","first-page":"407","author":"shoji","year":"2014","journal-title":"Theory of CMOS Digital Circuits and Circuit Failures"},{"journal-title":"Timing Analysis in Presence of Supply Voltage and Temperature Variations","year":"2017","key":"ref11"},{"key":"ref40","first-page":"150","article-title":"Electrical wire models","author":"rabaey","year":"2003","journal-title":"Digital Integrated Circuits A Design Perspective"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICEEOT.2016.7755624"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-9542-1"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/3DIC.2010.5751446"},{"key":"ref15","first-page":"180","author":"pavlidis","year":"2008","journal-title":"Three-Dimensional Integrated Circuit Design"},{"key":"ref16","first-page":"135","author":"salah","year":"2015","journal-title":"Arbitrary Modeling of TSVs for 3D Integrated Circuits"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2232708"},{"key":"ref18","first-page":"193","author":"pavlidis","year":"2008","journal-title":"Three-Dimensional Integrated Circuit Design"},{"key":"ref19","first-page":"519","article-title":"Three-dimensional cache design exploration using 3DCacti","author":"tsai","year":"2005","journal-title":"Proc Int Conf Comput Design VLSI Comput Process"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2015.113"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1049\/el.2012.0039"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2008.4616911"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1186\/s40064-016-2090-z"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICACCI.2014.6968252"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2693229"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/TEMC.2017.2685348"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2014.6942037"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2008.4681644"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/SIPS.2000.886761"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-9542-1"},{"key":"ref47","first-page":"773","article-title":"Combining static and dynamic defect-tolerance techniques for nanoscale memory systems","author":"biswas","year":"2007","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Design"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2298280"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2419255"},{"journal-title":"Inverter Speed and Propagation Delay","year":"2017","key":"ref44"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008282308028"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielaam\/92\/8396231\/8327893-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8396231\/08327893.pdf?arnumber=8327893","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,8]],"date-time":"2022-04-08T18:48:32Z","timestamp":1649443712000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8327893\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,7]]},"references-count":61,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2018.2809961","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2018,7]]}}}