{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,7]],"date-time":"2025-11-07T09:23:02Z","timestamp":1762507382168,"version":"3.37.3"},"reference-count":26,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2018,7,1]],"date-time":"2018-07-01T00:00:00Z","timestamp":1530403200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2018,7,1]],"date-time":"2018-07-01T00:00:00Z","timestamp":1530403200000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2018,7,1]],"date-time":"2018-07-01T00:00:00Z","timestamp":1530403200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2018,7,1]],"date-time":"2018-07-01T00:00:00Z","timestamp":1530403200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"NSF-CNS","award":["1615774"],"award-info":[{"award-number":["1615774"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2018,7]]},"DOI":"10.1109\/tvlsi.2018.2814544","type":"journal-article","created":{"date-parts":[[2018,3,29]],"date-time":"2018-03-29T18:06:05Z","timestamp":1522346765000},"page":"1290-1300","source":"Crossref","is-referenced-by-count":14,"title":["Design and Analysis of Energy-Efficient and Reliable 3-D ReRAM Cross-Point Array System"],"prefix":"10.1109","volume":"26","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0028-6059","authenticated-orcid":false,"given":"Manqing","family":"Mao","sequence":"first","affiliation":[]},{"given":"Shimeng","family":"Yu","sequence":"additional","affiliation":[]},{"given":"Chaitali","family":"Chakrabarti","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"497","article-title":"HfOx based vertical resistive random access memory for cost-effective 3D cross-point architecture without cell selector","author":"chen","year":"2012","journal-title":"IEDM Tech Dig"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2013.6724693"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2014.6742992"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2013.6582122"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2553123"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2651647"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2185930"},{"key":"ref17","first-page":"1","author":"yu","year":"2016","journal-title":"Resistive Random Access Memory (RRAM) From Devices to Array Architectures"},{"key":"ref18","first-page":"1","article-title":"Device-architecture co-design for hyperdimensional computing with 3D vertical resistive switching random access memory (3D VRRAM)","author":"li","year":"2017","journal-title":"Proc IEEE Symp VLSI Technol"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1038\/srep13504"},{"key":"ref4","first-page":"338","article-title":"A 16 Gb ReRAM with 200 MB\/s write and 1 GB\/s read in 27 nm technology","author":"fackenthal","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref3","first-page":"434","article-title":"A 0.5 V 4 Mb logic-process compatible embedded resistive RAM (ReRAM) in 65 nm CMOS using low-voltage current-mode sensing scheme with 45 ns random read time","author":"chang","year":"2012","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2215121"},{"key":"ref5","first-page":"210","article-title":"A 130.7 mm\n$^{2}$\n 2-layer 32 Gb ReRAM memory device in 24 nm technology","author":"liu","year":"2013","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref8","first-page":"1","article-title":"Full chip integration of 3-D cross-point ReRAM with leakage-compensating write driver and disturbance-aware sense amplifier","author":"lee","year":"2016","journal-title":"Proc IEEE Symp VLSI Circuits (VLSI)"},{"key":"ref7","first-page":"260","article-title":"A \n$0.13~\\mu \\text{m}$\n 64 Mb multi-layered conductive metal-oxide memory","author":"chevallier","year":"2010","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref2","first-page":"200","article-title":"A 4 Mb embedded SLC resistive-RAM macro with 7.2 ns read-write random-access time and 160 ns MLC-access capability","author":"sheu","year":"2011","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref9","first-page":"153","article-title":"Multi-layer sidewall WO\n$_{X}$\n resistive memory suitable for 3D ReRAM","author":"chien","year":"2012","journal-title":"VLSI Symp Tech Dig"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2012.2190369"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2015.2492421"},{"journal-title":"Predictive Technology Model 22 nm LP V2 1","year":"2008","key":"ref22"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2012.2210856"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/2333660.2333712"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2015.2426531"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.2006.354942"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056056"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielaam\/92\/8396231\/8327856-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8396231\/08327856.pdf?arnumber=8327856","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,8]],"date-time":"2022-04-08T18:48:32Z","timestamp":1649443712000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8327856\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,7]]},"references-count":26,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2018.2814544","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2018,7]]}}}