{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,8,21]],"date-time":"2026-08-21T13:19:14Z","timestamp":1787318354009,"version":"build-2736575974"},"reference-count":24,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2018,7,1]],"date-time":"2018-07-01T00:00:00Z","timestamp":1530403200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2018,7,1]],"date-time":"2018-07-01T00:00:00Z","timestamp":1530403200000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2018,7,1]],"date-time":"2018-07-01T00:00:00Z","timestamp":1530403200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2018,7,1]],"date-time":"2018-07-01T00:00:00Z","timestamp":1530403200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000001","name":"NSF I\/UCRC Center for Embedded Systems through NSF","doi-asserted-by":"publisher","award":["1230401"],"award-info":[{"award-number":["1230401"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"NSF I\/UCRC Center for Embedded Systems through NSF","doi-asserted-by":"publisher","award":["1237856"],"award-info":[{"award-number":["1237856"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"NSF I\/UCRC Center for Embedded Systems through NSF","doi-asserted-by":"publisher","award":["1701241"],"award-info":[{"award-number":["1701241"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"NSF I\/UCRC Center for Embedded Systems through NSF","doi-asserted-by":"publisher","award":["1361926"],"award-info":[{"award-number":["1361926"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"NSF I\/UCRC Center for Embedded Systems through NSF","doi-asserted-by":"publisher","award":["1535669"],"award-info":[{"award-number":["1535669"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"NSF I\/UCRC Center for Embedded Systems through NSF","doi-asserted-by":"publisher","award":["1652866"],"award-info":[{"award-number":["1652866"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"NSF I\/UCRC Center for Embedded Systems through NSF","doi-asserted-by":"publisher","award":["1715443"],"award-info":[{"award-number":["1715443"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Intel Labs"},{"DOI":"10.13039\/100014553","name":"Samsung Advanced Institute of Technology","doi-asserted-by":"crossref","id":[{"id":"10.13039\/100014553","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2018,7]]},"DOI":"10.1109\/tvlsi.2018.2815603","type":"journal-article","created":{"date-parts":[[2018,4,3]],"date-time":"2018-04-03T14:58:06Z","timestamp":1522767486000},"page":"1354-1367","source":"Crossref","is-referenced-by-count":325,"title":["Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA"],"prefix":"10.1109","volume":"26","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-2670-524X","authenticated-orcid":false,"given":"Yufei","family":"Ma","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yu","family":"Cao","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9278-2959","authenticated-orcid":false,"given":"Sarma","family":"Vrudhula","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jae-sun","family":"Seo","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2934583.2934644"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2847263.2847276"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021738"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2705069"},{"key":"ref14","first-page":"1","article-title":"Scalable and modularized RTL compilation of convolutional neural networks onto FPGA","author":"ma","year":"2016","journal-title":"Proc Int Conf Field Program Logic (FPL)"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021736"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.23919\/FPL.2017.8056824"},{"key":"ref17","first-page":"1","article-title":"A high performance FPGA-based accelerator for large-scale convolutional neural networks","author":"li","year":"2016","journal-title":"Proc Int Conf Field Program Logic (FPL)"},{"key":"ref18","first-page":"1393","article-title":"Efficient FPGA Acceleration of Convolutional Neural Networks Using Logical-3D Compute Array","author":"atul rahman","year":"2016","journal-title":"Design Automation Test in Europe Conference Exhibition (DATE)"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2016.7428073"},{"key":"ref4","article-title":"Very deep convolutional networks for large-scale image recognition","author":"simonyan","year":"2015","journal-title":"Proc Int Conf Learn Represent"},{"key":"ref3","author":"lin","year":"2014","journal-title":"Network in Network"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/197405.197406"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001177"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2616357"},{"key":"ref2","first-page":"1097","article-title":"ImageNet classification with deep convolutional neural networks","author":"krizhevsky","year":"2012","journal-title":"Proc Adv Neural Inf Process Syst (NIPS)"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/s11263-015-0816-y"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2684746.2689060"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001163"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/92.784091"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2735490"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062207"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2017.25"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielaam\/92\/8396231\/8330049-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8396231\/08330049.pdf?arnumber=8330049","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,8]],"date-time":"2022-04-08T14:48:32Z","timestamp":1649429312000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8330049\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,7]]},"references-count":24,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2018.2815603","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,7]]}}}