{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,3]],"date-time":"2026-03-03T16:29:47Z","timestamp":1772555387119,"version":"3.50.1"},"reference-count":34,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2018,7,1]],"date-time":"2018-07-01T00:00:00Z","timestamp":1530403200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2018,7]]},"DOI":"10.1109\/tvlsi.2018.2816914","type":"journal-article","created":{"date-parts":[[2018,3,29]],"date-time":"2018-03-29T18:06:05Z","timestamp":1522346765000},"page":"1368-1376","source":"Crossref","is-referenced-by-count":43,"title":["Secure Double Rate Registers as an RTL Countermeasure Against Power Analysis Attacks"],"prefix":"10.1109","volume":"26","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-6947-4410","authenticated-orcid":false,"given":"Davide","family":"Bellizia","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Simone","family":"Bongiovanni","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pietro","family":"Monsurro","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5650-8212","authenticated-orcid":false,"given":"Giuseppe","family":"Scotti","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alessandro","family":"Trifiletti","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Francesco Bruno","family":"Trotta","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-662-48324-4_25"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-57339-7_5"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2008.149"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.870913"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-64647-3_6"},{"key":"ref10","first-page":"403","article-title":"A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards","author":"tiri","year":"2002","journal-title":"Proc ESSCIRC"},{"key":"ref11","first-page":"172","article-title":"Masked dual-rail pre-charge logic: DPA-resistance without routing constraints","volume":"3659","author":"popp","year":"2005","journal-title":"Cryptographic Hardware and Embedded Systems&#x2014;CHES"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2046505"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1007\/s13389-015-0096-z"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-30205-6_50"},{"key":"ref15","first-page":"403","article-title":"A logic level countermeasure against CPA side channel attacks on AES","author":"menicocci","year":"2013","journal-title":"Proc Int Conf Mixed Design Integr Circuits Syst (MIXDES'06)"},{"key":"ref16","first-page":"216","article-title":"Secure AES hardware module for resource constrained devices","volume":"3313","author":"trichina","year":"2004","journal-title":"Proc Eur Workshop Secur Ad-Hoc Sensor Networks"},{"key":"ref17","first-page":"56","article-title":"FPGA implementations of the AES masked against power analysis attacks","author":"regazzoni","year":"2011","journal-title":"Constructive Side-Channel Analysis and Secure Design"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1007\/11605805_14"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2015.2452371"},{"key":"ref4","year":"2013","journal-title":"International Technology Roadmap for Semiconductors"},{"key":"ref28","first-page":"427","article-title":"Information theoretic evaluation of side-channel resistant logic styles","author":"mac\u00e9","year":"2007","journal-title":"Proc 9th Int Workshop Cryptograph Hardw Embed Syst (CHES)"},{"key":"ref3","author":"mangard","year":"2008","journal-title":"Power Analysis Attacks Revealing the Secrets of Smart Cards"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1007\/11545262_26"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2007.178"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-20465-4_8"},{"key":"ref29","year":"2011"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2016.2563322"},{"key":"ref7","article-title":"Lightweight cryptography: Cryptographic engineering for a pervasive world","author":"poschmann","year":"2009"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-48405-1_25"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-68697-5_9"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1268856"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2016.2546387"},{"key":"ref22","first-page":"151","article-title":"Investigations of power analysis attacks on smartcards","author":"messerges","year":"1999","journal-title":"Proc USENIX Workshop Smartcard Technol"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2005.1465395"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-45472-1_12"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-44499-8_20"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-01001-9_26"},{"key":"ref25","first-page":"16","article-title":"Correlation power analysis with a leakage model","volume":"3156","author":"brier","year":"2004","journal-title":"Proc CHES"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8396231\/08327903.pdf?arnumber=8327903","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:16:01Z","timestamp":1642004161000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8327903\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,7]]},"references-count":34,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2018.2816914","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,7]]}}}