{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:21:57Z","timestamp":1740133317693,"version":"3.37.3"},"reference-count":25,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2018,8,1]],"date-time":"2018-08-01T00:00:00Z","timestamp":1533081600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100003711","name":"Ministry of Science and Technology","doi-asserted-by":"publisher","award":["105-2221-E-001-013-MY3","105-2221-E-001-004-MY2","106-3114-E-002-008","104-2221-E-002-219-MY3","106-2221-E-002-037-MY3"],"award-info":[{"award-number":["105-2221-E-001-013-MY3","105-2221-E-001-004-MY2","106-3114-E-002-008","104-2221-E-002-219-MY3","106-2221-E-002-037-MY3"]}],"id":[{"id":"10.13039\/501100003711","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2018,8]]},"DOI":"10.1109\/tvlsi.2018.2819210","type":"journal-article","created":{"date-parts":[[2018,4,13]],"date-time":"2018-04-13T19:16:19Z","timestamp":1523646979000},"page":"1518-1530","source":"Crossref","is-referenced-by-count":5,"title":["Boosting NVDIMM Performance With a Lightweight Caching Algorithm"],"prefix":"10.1109","volume":"26","author":[{"given":"Che-Wei","family":"Tsao","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1282-2111","authenticated-orcid":false,"given":"Yuan-Hao","family":"Chang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tei-Wei","family":"Kuo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/NVMSA.2015.7304360"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783712"},{"journal-title":"Operating System Concepts","year":"2008","author":"silberschatz","key":"ref12"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/170036.170081"},{"journal-title":"A paging experiment with the Multics system","year":"1968","author":"corbat\u00f3","key":"ref14"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/800216.806596"},{"key":"ref16","first-page":"115","article-title":"Arc: A self-tuning, low overhead replacement cache","author":"megiddo","year":"2003","journal-title":"Proc USENIX Conf File and Storage Technologies (FAST)"},{"key":"ref17","first-page":"187","article-title":"Car: Clock with adaptive replacement","author":"bansal","year":"2004","journal-title":"Proc USENIX Conf File and Storage Technologies (FAST)"},{"key":"ref18","first-page":"439","article-title":"2Q: A low overhead high performance buffer management replacement algorithm","author":"johnson","year":"1994","journal-title":"Proc 20th Int Conf Very Large Data Bases (VLDB)"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/511399.511340"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2009.134"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2934583.2934632"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2008.4694174"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488936"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2380445.2380521"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1982185.1982264"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429400"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488938"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/RTCSA.2017.8046324"},{"journal-title":"NAND Flash Memory MT29F64G08AB[C\/E]BB MT29F128G08AE[C\/E]BB MT29F256G08AK[C\/E]BB","year":"2013","key":"ref20"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/BigData.2013.6691693"},{"journal-title":"NAND Flash Memory MT29F64G08CBAA[A\/B] MT29F128G08C[E\/F]AAA MT29F128G08CFAAB","year":"2009","key":"ref21"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/1065010.1065034"},{"key":"ref23","doi-asserted-by":"crossref","first-page":"229","DOI":"10.1145\/1508244.1508271","article-title":"A flash translation layer employing demand-based selective caching of page-level address mappings","author":"gupta","year":"2009","journal-title":"Proc ASPLOS"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2151018"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8419046\/08337123.pdf?arnumber=8337123","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,9,2]],"date-time":"2023-09-02T03:28:27Z","timestamp":1693625307000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8337123\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,8]]},"references-count":25,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2018.2819210","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2018,8]]}}}