{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:21:58Z","timestamp":1740133318337,"version":"3.37.3"},"reference-count":36,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2018,8,1]],"date-time":"2018-08-01T00:00:00Z","timestamp":1533081600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/Crown.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2018,8]]},"DOI":"10.1109\/tvlsi.2018.2821004","type":"journal-article","created":{"date-parts":[[2018,4,19]],"date-time":"2018-04-19T18:10:39Z","timestamp":1524161439000},"page":"1494-1507","source":"Crossref","is-referenced-by-count":2,"title":["Architectural Impacts of RFiop: RF to Address I\/O Pad and Memory Controller Scalability"],"prefix":"10.1109","volume":"26","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8336-9150","authenticated-orcid":false,"given":"Mario Donato","family":"Marino","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835945"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155664"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2011.5746409"},{"journal-title":"Nas Parallel Benchmarks","year":"2017","key":"ref30"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.62"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/2366231.2337207"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/2451512.2451543"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.35"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JLT.2014.2304305"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2008.4658639"},{"journal-title":"Moore&#x2019;s Law 40 Years and Counting","year":"2017","key":"ref13"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-6911-8_10"},{"article-title":"Quilt packaging: A novel high speed chip-to-chip communication parading for system-in-package","year":"2007","author":"liu","key":"ref15"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2012.6378638"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/1105734.1105748"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2006.82"},{"key":"ref19","first-page":"19","article-title":"Memory bandwidth and machine balance in current high performance computers","author":"mccalpin","year":"1995","journal-title":"IEEE TCCA Newslett"},{"journal-title":"The PChase Memory Benchmark Page","year":"2017","key":"ref28"},{"journal-title":"AMD Reveals Details about Bulldozer Microprocessors","year":"2011","key":"ref4"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.44"},{"journal-title":"ITRS Home","year":"2017","key":"ref3"},{"journal-title":"Intel Fully Buffered DIMM","year":"2017","key":"ref6"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2008.4523070"},{"journal-title":"Rambus","year":"2017","key":"ref8"},{"journal-title":"Hybrid Memory Cube Specification 1 0","year":"2017","key":"ref7"},{"journal-title":"Micron Manufactures DRAM Components Modules and NAND Flash","year":"2017","key":"ref2"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2009.5074166"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.15"},{"journal-title":"Ansoft High-Frequency Structure Simulator (HFSS)","year":"2017","key":"ref20"},{"key":"ref22","first-page":"1","article-title":"Off-chip coaxial-to-coplanar transition using MEMs trench","author":"abusultan","year":"2008","journal-title":"Proc 3D\/SiP Adv Packag Symp"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/2482767.2482803"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"journal-title":"CACTI 5 1","year":"2017","key":"ref23"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2011.6081428"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.876103"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8419046\/08341830.pdf?arnumber=8341830","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:09:02Z","timestamp":1642003742000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8341830\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,8]]},"references-count":36,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2018.2821004","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2018,8]]}}}