{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,4]],"date-time":"2025-07-04T04:11:43Z","timestamp":1751602303777,"version":"3.41.0"},"reference-count":24,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2018,8,1]],"date-time":"2018-08-01T00:00:00Z","timestamp":1533081600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2018,8]]},"DOI":"10.1109\/tvlsi.2018.2821107","type":"journal-article","created":{"date-parts":[[2018,4,16]],"date-time":"2018-04-16T18:03:20Z","timestamp":1523901800000},"page":"1427-1437","source":"Crossref","is-referenced-by-count":3,"title":["Parallel and Serial Computation in Nanomagnet Logic: An Overview"],"prefix":"10.1109","volume":"26","author":[{"given":"Davide","family":"Giri","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Giovanni","family":"Causapruno","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4147-1098","authenticated-orcid":false,"given":"Fabrizio","family":"Riente","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2010.53"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2016.2619377"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2015.2407696"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.2007.32"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2009.21"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2011.2138714"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2363519"},{"key":"ref17","doi-asserted-by":"crossref","first-page":"65","DOI":"10.1145\/2770287.2770304","article-title":"A standard cell approach for MagnetoElastic NML circuits","author":"giri","year":"2014","journal-title":"IEEE\/ACM Int Symp on Nanoscale Arch (NANOARCH)"},{"key":"ref18","doi-asserted-by":"crossref","first-page":"274","DOI":"10.1007\/978-3-662-45908-9_12","article-title":"ToPoliNano: NanoMagnet logic circuits design and simulation","author":"vacca","year":"2014","journal-title":"Field-Coupled Nanocomputing"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2650983"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2302015"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"223","DOI":"10.1007\/978-3-662-45908-9_10","article-title":"NanoMagnet logic: An architectural level overview","author":"vacca","year":"2014","journal-title":"Field-Coupled Nanocomputing"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2013.2251422"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2014.2346208"},{"article-title":"Systolic algorithms for the CMU warp processor","year":"1978","author":"kung","key":"ref8"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/NANOARCH.2010.5510929"},{"key":"ref2","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-662-45908-9_12","article-title":"Electric clock for NanoMagnet logic circuits","author":"vacca","year":"2014","journal-title":"Field-Coupled Nanocomputing"},{"article-title":"Limits of CMOS Technology scaling and technologies beyond-CMOS","year":"2005","author":"rairigh","key":"ref1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2011.234"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1126\/science.287.5457.1466"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/IWCE.2010.5677954"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2010.2056697"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1088\/0953-8984\/23\/49\/493202"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2014.2333657"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8419046\/08338338.pdf?arnumber=8338338","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,3]],"date-time":"2025-07-03T18:20:52Z","timestamp":1751566852000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8338338\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,8]]},"references-count":24,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2018.2821107","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2018,8]]}}}