{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:21:58Z","timestamp":1740133318157,"version":"3.37.3"},"reference-count":12,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2018,8,1]],"date-time":"2018-08-01T00:00:00Z","timestamp":1533081600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100003593","name":"Conselho Nacional de Desenvolvimento Cient\u00edfico e Tecnol\u00f3gico","doi-asserted-by":"publisher","award":["460205\/2014-5","401839\/2013-3"],"award-info":[{"award-number":["460205\/2014-5","401839\/2013-3"]}],"id":[{"id":"10.13039\/501100003593","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2018,8]]},"DOI":"10.1109\/tvlsi.2018.2821134","type":"journal-article","created":{"date-parts":[[2018,4,19]],"date-time":"2018-04-19T18:10:39Z","timestamp":1524161439000},"page":"1609-1612","source":"Crossref","is-referenced-by-count":2,"title":["A DfT Insertion Methodology to Scannable Q-Flop Elements"],"prefix":"10.1109","volume":"26","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1445-7610","authenticated-orcid":false,"given":"Leonardo R.","family":"Juracy","sequence":"first","affiliation":[]},{"given":"Matheus T.","family":"Moreira","sequence":"additional","affiliation":[]},{"given":"Felipe A.","family":"Kuentzer","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8432-3162","authenticated-orcid":false,"given":"Alexandre M.","family":"Amory","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ARVLSI.1995.515612"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1995.519945"},{"journal-title":"DFTMAX Design-for-Test User Guide Version N-2017 09-SP4","year":"2017","key":"ref10"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2011.6081379"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2589548"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2015.13"},{"article-title":"TEA extensions","year":"1997","author":"needham","key":"ref12"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.203"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2405614"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/12.2252"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2007.15"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2007.151"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8419046\/08341809.pdf?arnumber=8341809","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:16:08Z","timestamp":1642004168000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8341809\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,8]]},"references-count":12,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2018.2821134","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2018,8]]}}}