{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,11]],"date-time":"2025-10-11T05:46:09Z","timestamp":1760161569209,"version":"3.37.3"},"reference-count":17,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2018,9,1]],"date-time":"2018-09-01T00:00:00Z","timestamp":1535760000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100003725","name":"National Research Foundation of Korea","doi-asserted-by":"publisher","award":["2016R1A2B4011799"],"award-info":[{"award-number":["2016R1A2B4011799"]}],"id":[{"id":"10.13039\/501100003725","id-type":"DOI","asserted-by":"publisher"}]},{"name":"ICT Research and Development program of MSIP\/IITP","award":["2016(R7177-16-0233)"],"award-info":[{"award-number":["2016(R7177-16-0233)"]}]},{"DOI":"10.13039\/100004358","name":"Samsung","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100004358","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2018,9]]},"DOI":"10.1109\/tvlsi.2018.2824818","type":"journal-article","created":{"date-parts":[[2018,4,20]],"date-time":"2018-04-20T18:08:10Z","timestamp":1524247690000},"page":"1802-1806","source":"Crossref","is-referenced-by-count":3,"title":["ICS: Interrupt-Based Channel Sneaking for Maximally Exploiting Die-Level Parallelism of NAND Flash-Based Storage Devices"],"prefix":"10.1109","volume":"26","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8025-6791","authenticated-orcid":false,"given":"Juhyung","family":"Hong","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sangwoo","family":"Han","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Young Min","family":"Park","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2013-8763","authenticated-orcid":false,"given":"Eui-Young","family":"Chung","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2010.209"},{"key":"ref11","first-page":"1","article-title":"Architectural considerations for optimizing SSDs","author":"abraham","year":"2014","journal-title":"Proc Flash Memory Summit"},{"key":"ref12","first-page":"1","article-title":"System design for mainstream TLC SSD meeting the performance challenge","author":"sharma","year":"2014","journal-title":"Proc Flash Memory Summit"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2013.12.002"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2409055"},{"key":"ref15","doi-asserted-by":"crossref","first-page":"204","DOI":"10.1109\/JSSC.2015.2474117","article-title":"A 128 Gb 3b\/cell V-NAND flash memory with 1 Gb\/s I\/O rate","volume":"51","author":"jeong","year":"2016","journal-title":"IEEE J Solid-State Circuits"},{"journal-title":"Storage Networking Industry Association","year":"2017","key":"ref16"},{"journal-title":"UMass Trace Repository","year":"2017","key":"ref17"},{"key":"ref4","first-page":"404","article-title":"Physically addressed queueing (PAQ): Improving parallelism in solid state disks","author":"jung","year":"2012","journal-title":"Proc IEEE Annu Int Symp Comput Arch (ISCA)"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2016.2588491"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/HPCC.and.EUC.2013.199"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MSST.2013.6558433"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2016.2636840"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MSST.2014.6855544"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2012.60"},{"journal-title":"Specifications&#x2014;ONFi","year":"2017","key":"ref1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3037697.3037728"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8444866\/08344560.pdf?arnumber=8344560","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,26]],"date-time":"2022-01-26T15:36:13Z","timestamp":1643211373000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8344560\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,9]]},"references-count":17,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2018.2824818","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2018,9]]}}}