{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,28]],"date-time":"2025-11-28T12:24:02Z","timestamp":1764332642819,"version":"3.37.3"},"reference-count":28,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2018,9,1]],"date-time":"2018-09-01T00:00:00Z","timestamp":1535760000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2018,9,1]],"date-time":"2018-09-01T00:00:00Z","timestamp":1535760000000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2018,9,1]],"date-time":"2018-09-01T00:00:00Z","timestamp":1535760000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2018,9,1]],"date-time":"2018-09-01T00:00:00Z","timestamp":1535760000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CCF-1350451"],"award-info":[{"award-number":["CCF-1350451"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CNS-1715286"],"award-info":[{"award-number":["CNS-1715286"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100004351","name":"Cisco Systems","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100004351","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2018,9]]},"DOI":"10.1109\/tvlsi.2018.2827238","type":"journal-article","created":{"date-parts":[[2018,5,24]],"date-time":"2018-05-24T19:23:21Z","timestamp":1527189801000},"page":"1647-1658","source":"Crossref","is-referenced-by-count":19,"title":["Duty-Cycle-Based Controlled Physical Unclonable Function"],"prefix":"10.1109","volume":"26","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-9989-4096","authenticated-orcid":false,"given":"Mahmood J.","family":"Azhar","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7126-5984","authenticated-orcid":false,"given":"Fathi","family":"Amsaad","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Selcuk","family":"Kose","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"crossref","first-page":"329","DOI":"10.1109\/PRIME.2013.6603178","article-title":"Dynamic programming based grouping method for RO-PUFs","author":"k\u00f6m\u00fcrc\u00fc","year":"2013","journal-title":"Proc Ph D Rese Microelectron Electron Conf (PRIME)"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2010.5513105"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1284680.1284683"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JIOT.2017.2703088"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2013.6572325"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2016.7539093"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2011.88"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2017.121"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2294402"},{"journal-title":"Predictive Technology Model (PTM)","year":"2008","key":"ref19"},{"journal-title":"High Performance Integrated Circuits","year":"2012","author":"salman","key":"ref28"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2014.2320516"},{"journal-title":"Routing Congestion in VLSI Circuits Estimation and Optimization","year":"2007","author":"saxena","key":"ref27"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"9","DOI":"10.1145\/1278480.1278484","article-title":"physical unclonable functions for device authentication and secret key generation","author":"suh","year":"2007","journal-title":"2007 44th ACM\/IEEE Design Automation Conference DAC"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2007.378156"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.907047"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1502781.1502786"},{"journal-title":"Introduction to Hardware Security and Trust","year":"2011","author":"tehranipoor","key":"ref7"},{"key":"ref2","first-page":"125","article-title":"Low cost attacks on tamper resistant devices","author":"anderson","year":"1997","journal-title":"Proc 5th Int Workshop Secur Protocols"},{"key":"ref9","first-page":"237","article-title":"Modeling attacks on physical unclonable functions","author":"r\u00fchrmair","year":"2010","journal-title":"Proc 17th ACM Conf Comput Commun Secur"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1126\/science.1074376"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2013.6674686"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1007\/s00145-010-9088-4"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.840399"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2011.82"},{"key":"ref23","doi-asserted-by":"crossref","first-page":"1143","DOI":"10.1109\/TCAD.2015.2424955","article-title":"A low-power hybrid RO PUF with improved thermal stability for lightweight applications","volume":"34","author":"cao","year":"2015","journal-title":"IEEE Trans Comput -Aided Design Integr Circuits Syst"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2012.6341361"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2015.2440739"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielaam\/92\/8444866\/8365151-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8444866\/08365151.pdf?arnumber=8365151","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,8]],"date-time":"2022-04-08T18:48:31Z","timestamp":1649443711000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8365151\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,9]]},"references-count":28,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2018.2827238","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2018,9]]}}}