{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,25]],"date-time":"2025-10-25T19:06:42Z","timestamp":1761419202314,"version":"3.37.3"},"reference-count":29,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2018,9,1]],"date-time":"2018-09-01T00:00:00Z","timestamp":1535760000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2018,9]]},"DOI":"10.1109\/tvlsi.2018.2828301","type":"journal-article","created":{"date-parts":[[2018,4,30]],"date-time":"2018-04-30T18:41:28Z","timestamp":1525113688000},"page":"1788-1801","source":"Crossref","is-referenced-by-count":4,"title":["Cascade and <i>LC<\/i> Ladder-Based Filter Realizations Using Synchronous Time-Mode Signal Processing"],"prefix":"10.1109","volume":"26","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-7187-0503","authenticated-orcid":false,"given":"Moataz","family":"Abdelfattah","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4880-0272","authenticated-orcid":false,"given":"Gordon","family":"Roberts","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2009.5118255"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2225738"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISOCC.2012.6406888"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/DCIS.2014.7035586"},{"key":"ref14","first-page":"766","article-title":"A single chip fluorometer for fluorescence lifetime spectroscopy in 65 nm CMOS","author":"guo","year":"2011","journal-title":"Proc IEEE Sensors"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2012.2190669"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/19.963197"},{"key":"ref17","doi-asserted-by":"crossref","first-page":"722","DOI":"10.1109\/JSSC.2004.826329","article-title":"A low-noise low-offset capacitive sensing amplifier for a 50-\n$\\mu \\text{g}\/\\sqrt {Hz}$\n monolithic CMOS MEMS accelerometer","volume":"39","author":"wu","year":"2004","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1049\/el:19660190"},{"journal-title":"Electronic Filter Design Handbook","year":"1995","author":"williams","key":"ref19"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2024801"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2321195"},{"key":"ref27","first-page":"360","article-title":"A 0.55 V 61 dB-SNR 67 dB-SFDR 7 MHz \n$4^{\\mathrm{ th}}$\n-order butterworth filter using ring-oscillator-based integrators in 90 nm CMOS","author":"drost","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"journal-title":"CMOS Sigma-Delta Converters Practical Design Guide","year":"2013","author":"jos\u00e9","key":"ref3"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2013.2265976"},{"key":"ref29","first-page":"506","article-title":"A 0.5 V filter with PLL-based tuning in \n$0.18~\\mu \\text{m}$\n CMOS","volume":"1","author":"chatterjee","year":"2005","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref5","first-page":"480","article-title":"A 1.7 mW 11 b 1-1-1 MASH \n$\\Delta \\Sigma $\n time-to-digital converter","author":"cao","year":"2011","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2014.6865587"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1049\/el.2011.1406"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2742518"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2016.2636327"},{"key":"ref1","first-page":"174","article-title":"A 2.7-to-4.3 GHz, 0.16 psrms-jitter, ?246.8 dB-FOM, digital fractional-N sampling PLL in 28 nm CMOS","author":"gao","year":"2016","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCS.1975.1084021"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2359656"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCS.1986.1085984"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2015.7338426"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2336532"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2016.7472937"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2715885"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8444866\/08352760.pdf?arnumber=8352760","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,26]],"date-time":"2022-01-26T16:02:22Z","timestamp":1643212942000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8352760\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,9]]},"references-count":29,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2018.2828301","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2018,9]]}}}