{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,2]],"date-time":"2025-04-02T09:04:48Z","timestamp":1743584688622,"version":"3.37.3"},"reference-count":39,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2018,9,1]],"date-time":"2018-09-01T00:00:00Z","timestamp":1535760000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61474092"],"award-info":[{"award-number":["61474092"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2018,9]]},"DOI":"10.1109\/tvlsi.2018.2832472","type":"journal-article","created":{"date-parts":[[2018,5,18]],"date-time":"2018-05-18T19:18:17Z","timestamp":1526671097000},"page":"1763-1776","source":"Crossref","is-referenced-by-count":6,"title":["A Low-Power Pipelined-SAR ADC Using Boosted Bucket-Brigade Device for Residue Charge Processing"],"prefix":"10.1109","volume":"26","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-2746-1846","authenticated-orcid":false,"given":"Hong","family":"Zhang","sequence":"first","affiliation":[]},{"given":"Junqiang","family":"Sun","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1877-1968","authenticated-orcid":false,"given":"Jie","family":"Zhang","sequence":"additional","affiliation":[]},{"given":"Ruizhi","family":"Zhang","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0977-7516","authenticated-orcid":false,"given":"Anthony","family":"Chan Carusone","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2042254"},{"key":"ref38","first-page":"246","article-title":"A 65fJ\/conversion-step 0-to-50 MS\/s 0-to-0.7 mW 9b charge-sharing SAR ADC in 90 nm digital CMOS","author":"craninckx","year":"2007","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2008.4586015"},{"article-title":"Boosted charge transfer circuit","year":"2013","author":"anthony","key":"ref32"},{"key":"ref31","doi-asserted-by":"crossref","first-page":"339","DOI":"10.1109\/TCSII.2014.2312642","article-title":"A 6-bit 1-GS\/s Two-Step SAR ADC in 40-nm CMOS","volume":"61","author":"tai","year":"2014","journal-title":"IEEE Trans Circuits Syst II Exp Briefs"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2016.2608908"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/ICSICT.2014.7021239"},{"article-title":"Common-mode charge control in a pipelined charge-domain signal-processing circuit","year":"2009","author":"anthony","key":"ref36"},{"key":"ref35","first-page":"98c","article-title":"A 12-bit, 200-MS\/s, 11.5-mW pipeline ADC using a pulsed bucket brigade front-end","author":"dolev","year":"2013","journal-title":"Proc Symp VLSI Circuits"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/csics.2009.5315608"},{"key":"ref10","first-page":"265","article-title":"A 12-bit 110MS\/s 4-stage single-opamp pipelined SAR ADC with ratio-based GEC technique","author":"wang","year":"2012","journal-title":"Proc ESSCIRC"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2016.2546856"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2014.6942059"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2010.5619890"},{"key":"ref14","first-page":"1","article-title":"A 9.15 mW 0.22 mm2 10 b 204 MS\/s pipelined SAR ADC in 65 nm CMOS","author":"jeon","year":"2010","journal-title":"Proc IEEE Custom Integr Circuits Conf"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2211695"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2361774"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2014.6858451"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2576468"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2464684"},{"key":"ref28","first-page":"268c","article-title":"A 2.1 mW 11b 410 MS\/s dynamic pipelined SAR ADC with background calibration in 28 nm digital CMOS","author":"verbruggen","year":"2013","journal-title":"Proc Symp VLSI Circuits"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2015.7338385"},{"key":"ref27","first-page":"466","article-title":"A 1.7 mW 11b 250 MS\/s \n$2\\times $\n interleaved fully dynamic pipelined SAR ADC in 40 nm digital CMOS","author":"verbruggen","year":"2012","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2048498"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2108133"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2015.2503705"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2075310"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2016.2554858"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2361339"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2331354"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2126390"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2377431"},{"key":"ref20","first-page":"169","article-title":"A 12b 180 MS\/s 0.068 mm2 pipelined-SAR ADC with merged-residue DAC for noise reduction","author":"zhong","year":"2016","journal-title":"Proc Conf 42nd Eur Solid-State Circuits Conf (ESSCIRC)"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2463094"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2015.7387462"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2217865"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2384025"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2299632"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2014.6945993"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8444866\/08361054.pdf?arnumber=8361054","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,26]],"date-time":"2022-01-26T12:34:48Z","timestamp":1643200488000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8361054\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,9]]},"references-count":39,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2018.2832472","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2018,9]]}}}