{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,3]],"date-time":"2025-11-03T13:38:19Z","timestamp":1762177099552,"version":"3.37.3"},"reference-count":43,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2018,10,1]],"date-time":"2018-10-01T00:00:00Z","timestamp":1538352000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2018,10,1]],"date-time":"2018-10-01T00:00:00Z","timestamp":1538352000000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2018,10,1]],"date-time":"2018-10-01T00:00:00Z","timestamp":1538352000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2018,10,1]],"date-time":"2018-10-01T00:00:00Z","timestamp":1538352000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CCF-1318603","CCF-1714161"],"award-info":[{"award-number":["CCF-1318603","CCF-1714161"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2018,10]]},"DOI":"10.1109\/tvlsi.2018.2832607","type":"journal-article","created":{"date-parts":[[2018,6,6]],"date-time":"2018-06-06T19:08:20Z","timestamp":1528312100000},"page":"1868-1880","source":"Crossref","is-referenced-by-count":14,"title":["Hybrid Monolithic 3-D IC Floorplanner"],"prefix":"10.1109","volume":"26","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-2828-0035","authenticated-orcid":false,"given":"Abdullah","family":"Guler","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1539-0369","authenticated-orcid":false,"given":"Niraj K.","family":"Jha","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"HotSpot 6 0 Temperature Modeling Tool","year":"2015","key":"ref39"},{"journal-title":"International Technology Roadmap for Semiconductor","year":"2013","key":"ref38"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2768330"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.907068"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.855969"},{"journal-title":"Synopsys Design Compiler","year":"2013","key":"ref30"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337541"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2006.77"},{"journal-title":"OpenSPARC T2","year":"2007","key":"ref35"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2017.8009189"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2260569"},{"article-title":"HotSpot 6.0: Validation, acceleration and extension","year":"2015","author":"zhang","key":"ref11"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2016.2523983"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/2491675"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2670508"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2648839"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1127908.1127994"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2009.4796505"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2055247"},{"key":"ref18","first-page":"1","article-title":"3D floorplanning considering vertically aligned rectilinear modules using T*-tree","author":"quiring","year":"2012","journal-title":"Proc IEEE Int 3D Syst Integr Conf"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2432141"},{"journal-title":"Sentaurus TCAD Tool Suite Version I-2013 12","year":"2013","key":"ref28"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2017.8268426"},{"journal-title":"14 nm FinFET Technology","year":"2015","key":"ref27"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382591"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2627369.2627642"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.1985.294681"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2002.1012669"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593188"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2012.6187545"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2014.6894407"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2293886"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/5.920580"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2967071"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2006.873612"},{"key":"ref21","first-page":"1185","article-title":"3DHLS: Incorporating high-level synthesis in physical planning of three-dimensional (3D) ICs","author":"chen","year":"2012","journal-title":"Proc Design Automat Test Europe Conf"},{"key":"ref24","first-page":"7.3.1","article-title":"Advances, challenges and opportunities in 3D CMOS sequential integration","author":"batude","year":"2011","journal-title":"IEDM Tech Dig"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2041850"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2201760"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/ICICDT.2008.4567296"},{"journal-title":"Intel 14nm Technology","year":"2014","key":"ref26"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2564300"},{"key":"ref43","first-page":"2","article-title":"A 14 nm FinFET transistor-level 3D partitioning design to enable high-performance and low-cost monolithic 3D IC","author":"shi","year":"2016","journal-title":"IEDM Tech Dig"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielaam\/92\/8472222\/8374061-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8472222\/08374061.pdf?arnumber=8374061","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,8]],"date-time":"2022-04-08T18:48:33Z","timestamp":1649443713000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8374061\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,10]]},"references-count":43,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2018.2832607","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2018,10]]}}}