{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:21:59Z","timestamp":1740133319945,"version":"3.37.3"},"reference-count":19,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2018,10,1]],"date-time":"2018-10-01T00:00:00Z","timestamp":1538352000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100003968","name":"Iran National Science Foundation","doi-asserted-by":"publisher","award":["95823741"],"award-info":[{"award-number":["95823741"]}],"id":[{"id":"10.13039\/501100003968","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2018,10]]},"DOI":"10.1109\/tvlsi.2018.2835833","type":"journal-article","created":{"date-parts":[[2018,5,28]],"date-time":"2018-05-28T18:25:41Z","timestamp":1527531941000},"page":"1845-1853","source":"Crossref","is-referenced-by-count":0,"title":["Scalable Symbolic Simulation-Based Automatic Correction of Modern Processors"],"prefix":"10.1109","volume":"26","author":[{"given":"Fatemeh","family":"Refan","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4436-4597","authenticated-orcid":false,"given":"Bijan","family":"Alizadeh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zainalabedin","family":"Navabi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1587\/transinf.E97.D.852"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2762006"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2010.74"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-31612-8_10"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2012.55"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-26287-1_16"},{"key":"ref16","first-page":"1","article-title":"Deciding CLU logic formulas via Boolean and pseudo-Boolean encodings","author":"bryant","year":"2002","journal-title":"Proc 1st Int Workshop Constraints Formal Verification"},{"journal-title":"A User's Guide to UCLID Version 0 1","year":"0","author":"seshia","key":"ref17"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-58179-0_44"},{"journal-title":"MiniSat","year":"2016","key":"ref19"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2015.12.004"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2953879"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2348839.2348841"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2011.5770740"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2015.7116271"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-45657-0_7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2016.7428001"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2015.41"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.852031"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8472222\/08368095.pdf?arnumber=8368095","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:09:52Z","timestamp":1642003792000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8368095\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,10]]},"references-count":19,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2018.2835833","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2018,10]]}}}