{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,3]],"date-time":"2026-04-03T02:22:36Z","timestamp":1775182956812,"version":"3.50.1"},"reference-count":18,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2018,10,1]],"date-time":"2018-10-01T00:00:00Z","timestamp":1538352000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2018,10]]},"DOI":"10.1109\/tvlsi.2018.2842179","type":"journal-article","created":{"date-parts":[[2018,6,20]],"date-time":"2018-06-20T19:02:46Z","timestamp":1529521366000},"page":"1930-1938","source":"Crossref","is-referenced-by-count":24,"title":["A Single-Chip 4K 60-fps 4:2:2 HEVC Video Encoder LSI Employing Efficient Motion Estimation and Mode Decision Framework With Scalability to 8K"],"prefix":"10.1109","volume":"26","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-6837-0492","authenticated-orcid":false,"given":"Takayuki","family":"Onishi","sequence":"first","affiliation":[]},{"given":"Takashi","family":"Sano","sequence":"additional","affiliation":[]},{"given":"Yukikuni","family":"Nishida","sequence":"additional","affiliation":[]},{"given":"Kazuya","family":"Yokohari","sequence":"additional","affiliation":[]},{"given":"Ken","family":"Nakamura","sequence":"additional","affiliation":[]},{"given":"Koyo","family":"Nitta","sequence":"additional","affiliation":[]},{"given":"Kimiko","family":"Kawashima","sequence":"additional","affiliation":[]},{"given":"Jun","family":"Okamoto","sequence":"additional","affiliation":[]},{"given":"Naoki","family":"Ono","sequence":"additional","affiliation":[]},{"given":"Atsushi","family":"Sagata","sequence":"additional","affiliation":[]},{"given":"Hiroe","family":"Iwasaki","sequence":"additional","affiliation":[]},{"given":"Mitsuo","family":"Ikeda","sequence":"additional","affiliation":[]},{"given":"Atsushi","family":"Shimizu","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICIP.2014.7025242"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/EUSIPCO.2016.7760458"},{"key":"ref12","first-page":"54c","article-title":"Single-chip 4K 60 fps 4:2:2 HEVC video encoder LSI with 8K scalability","author":"onishi","year":"2015","journal-title":"Dig Symp VLSI Circuits"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/APCCAS.2014.7032708"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/DCC.2015.21"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2015.2511858"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/CoolChips.2017.7946382"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2014.6742917"},{"key":"ref18","first-page":"106","article-title":"An H.264\/AVC high422 profile and MPEG-2 422 profile encoder LSI for HDTV broadcasting infrastructures","author":"nitta","year":"2008","journal-title":"Dig Symp VLSI Circuits"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/IACC.2016.134"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2015.2389472"},{"key":"ref6","first-page":"188c","article-title":"A 1062 Mpixels\/s \n$8192\\times 4320$\np high efficiency video coding (H.265) encoder chip","author":"tsai","year":"2013","journal-title":"Dig Symp VLSI Circuits"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2386897"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/3036669.3038252"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICCE-Berlin.2016.7684727"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ICIP.2014.7025254"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2012.2221191"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICCE.2014.6775906"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8472222\/08388869.pdf?arnumber=8388869","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:09:52Z","timestamp":1642003792000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8388869\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,10]]},"references-count":18,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2018.2842179","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,10]]}}}