{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,8,18]],"date-time":"2026-08-18T00:38:12Z","timestamp":1787013492796,"version":"build-2736575974"},"reference-count":20,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2018,10,1]],"date-time":"2018-10-01T00:00:00Z","timestamp":1538352000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2018,10]]},"DOI":"10.1109\/tvlsi.2018.2849972","type":"journal-article","created":{"date-parts":[[2018,7,23]],"date-time":"2018-07-23T14:23:05Z","timestamp":1532355785000},"page":"2160-2164","source":"Crossref","is-referenced-by-count":2,"title":["Selecting Functional Test Sequences for Defect Diagnosis"],"prefix":"10.1109","volume":"26","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-5491-7282","authenticated-orcid":false,"given":"Irith","family":"Pomeranz","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2009.12"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/EDTC.1995.470385"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1997.639702"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1998.743306"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2002.1012632"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2016.7477279"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2014.2331559"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1998.743308"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894213"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2010.25"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2008.4700586"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2001.966682"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/EDTC.1997.582327"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041810"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2006.297674"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1268848"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1996.556969"},{"key":"ref1","author":"lam","year":"2008","journal-title":"Hardware Design Verification Simulation and Formal Method-Based Approaches"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2007.18"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.907229"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8472222\/08418476.pdf?arnumber=8418476","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:09:52Z","timestamp":1641985792000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8418476\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,10]]},"references-count":20,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2018.2849972","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,10]]}}}