{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,25]],"date-time":"2026-04-25T14:51:27Z","timestamp":1777128687931,"version":"3.51.4"},"reference-count":23,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2018,12,1]],"date-time":"2018-12-01T00:00:00Z","timestamp":1543622400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2018,12]]},"DOI":"10.1109\/tvlsi.2018.2865404","type":"journal-article","created":{"date-parts":[[2018,9,12]],"date-time":"2018-09-12T19:02:57Z","timestamp":1536778977000},"page":"2853-2862","source":"Crossref","is-referenced-by-count":34,"title":["A Hybrid Design Automation Tool for SAR ADCs in IoT"],"prefix":"10.1109","volume":"26","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-2632-5930","authenticated-orcid":false,"given":"Ming","family":"Ding","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6542-0001","authenticated-orcid":false,"given":"Pieter","family":"Harpe","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Guibin","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Benjamin","family":"Busze","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3256-6741","authenticated-orcid":false,"given":"Yao-Hong","family":"Liu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Christian","family":"Bachmann","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kathleen","family":"Philips","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3865-3050","authenticated-orcid":false,"given":"Arthur","family":"van Roermund","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.2009137"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2015.0062"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2474379"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2013.2268571"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2494063"},{"key":"ref15","first-page":"672","article-title":"A circuit-design-driven tool with a hybrid automation approach for SAR ADCs in IoT","author":"ding","year":"2018","journal-title":"Proceedings of the Design Automation and Test in Europe (DATE)"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2143870"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/4.760369"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2043893"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2042254"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/196244.196258"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/43.46777"},{"key":"ref6","first-page":"177","article-title":"A compiled 3.5fJ\/conv.step 9b 20MS\/s SAR ADC for wireless applications in 28 nm FDSOI","author":"wulff","year":"2016","journal-title":"Proc ESSCIRC"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TEVC.2003.808914"},{"key":"ref8","first-page":"1","article-title":"A fully automated verilog-to-layout synthesized ADC demonstrating 56dB-SNDR with 2 MHz-BW","author":"waters","year":"2015","journal-title":"Proc Solid-State Circuits Conf (A-SSCC)"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2269050"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/4.102664"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1987.1052861"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090670"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6177096"},{"key":"ref22","first-page":"74","article-title":"Analog module generators for silicon compilation","volume":"8","author":"kuhn","year":"1987","journal-title":"VLSI Syst Des"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2609849"},{"key":"ref23","author":"murmann","year":"2017","journal-title":"ADC Performance Survey 1997&#x2013;2013"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8554317\/08463579.pdf?arnumber=8463579","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,27]],"date-time":"2022-01-27T03:25:37Z","timestamp":1643253937000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8463579\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,12]]},"references-count":23,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2018.2865404","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,12]]}}}